Xilinx SP605 Hardware User's Manual page 22

Chapter 1: SP605 Evaluation Board
Table 1-7: Linear Flash Connections (Cont'd)
22
U1 FPGA Pin Schematic Net Name
E20
F22
F21
H19
H18
F20
G19
AA20 FPGA_D0_DIN_MISO_MISO1
R13
T14
AA6
AB6
Y5
AB5
W9
T7
U6
AB19
AA18
AB18
Y13
AA12
AB12
V13 FMC_PWR_GOOD_FLASH_RST_B
R20
P22
P21
T19
T18
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FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
FPGA_D1_MISO2
FPGA_D2_MISO3
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
FLASH_D8
FLASH_D9
FLASH_D10
FLASH_D11
FLASH_D12
FLASH_D13
FLASH_D14
FLASH_D15
FLASH_WE_B
FLASH_OE_B
FLASH_CE_B
FLASH_ADV_B
FLASH_WAIT
U25 BPI FLASH
Pin Number Pin Name
18 A18
17 A19
16 A20
11 A21
10 A22
9 A23
26 A24
34 DQ0
36 DQ1
39 DQ2
41 DQ3
47 DQ4
49 DQ5
51 DQ6
53 DQ7
35 DQ8
37 DQ9
40 DQ10
42 DQ11
48 DQ12
50 DQ13
52 DQ14
54 DQ15
44 RST_B
14 WE_B
32 OE_B
30 CE_B
46 ADV_B
56 WAIT
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019