Iic External Access Header; 8-Kb Nv Memory - Xilinx SP605 Hardware User's Manual

Table 1-19: IIC Bus Connections
Notes:
1. U4 IIC bus signals are resistively coupled with 0Ω resistors
2. Legend

IIC External Access Header

J45 (see
the SP605 IIC bus. When connected, the external device can be accessed via IIC commands
using IIC_SDA_MAIN and IIC_SCL_MAIN.

8-Kb NV Memory

The SP605 hosts a 8-Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage
memory device (U4). The IIC address of U4 is 0b1010100, and U4 is not write protected
(WP pin 7 is tied to GND).
The IIC memory is shown in
X-Ref Target - Figure 1-12
IIC_SCL_MAIN
IIC_SDA_MAIN
2
External Access
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
Schematic
U1 FPGA Pin
Netname
R22 IIC_SDA_MAIN
T21 IIC_SCL_MAIN
AA4 IIC_SDA_DVI
W13 IIC_SCL_DVI
E6 IIC_SDA_SFP
E5 IIC_SCL_SFP
J2, FMC LPC Connector
P2, SFP Module Connector
P3, DVI Connector
Qn.n, Level-Shifting Transistor
U31, Chrontel CH7301C
Figure 1-12) is a two-pin header that allows external IIC devices to be connected to
1
2
J45
1
H-1X2
Header
Figure 1-12: IIC Memory U4
www.xilinx.com
Connected To
(1)
J2.C31, U4.5
(1)
J2.C30, U4.6
Q8.2, U31.14
Q7.2, U31.15
P2.4
P2.5
Figure 1-12.
VCC3V3
1 1
R6 R5 R50
1.0K 1.0K 50
5% 5% 1%
1/10W 2 1/10W 2 1/16W
6
5
1
2
3
M24C08-WDW6TP
1
R216
DNP
2
Detailed Description
Level-Shifted Level-Shifted
Connection Net Name
–
–
Q8.3, P3.7 IIC_SDA_DVI_F
Q7.3, P3.6 IIC_CLK_DVI_F
–
–
IIC Address 0b1010100
VCC3V3
U4
SCL
7
SDA WP
1 C40
0.1UF
A0
2
X5R
8
A1 VCC
4 10V
A2 GND
UG526_12 _012611
–
–
–
–
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