Revision History - Xilinx SP605 Hardware User's Manual

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Revision History

The following table shows the revision history for this document.
Date Version
10/07/09 1.0
11/09/09 1.1
02/01/10 1.1.1
05/18/10 1.2
06/16/10 1.3
09/24/10 1.4
02/16/11 1.5
SP605 Hardware User Guide
Initial Xilinx release.
• Updated Figure 1-17 and
• Changed speed grade from -2 to -3.
• Miscellaneous typographical edits.
Minor typographical edits to
Updated Figure 1-2. Added Note 6 to
SFP_TX_DISABLE in Table
57.1 FMC LPC Connector. Updated U1 FPGA Pin column for FMC_LA00_CC_P/N in
Table 1-28. Updated description of PMBus Pod and TI Fusion Digital Power Software
GUI in Onboard Power Regulation. Updated
Connector Pinout, and Appendix C, Xilinx Design
Updated 2. 128 MB DDR3 Component
Updated description of Fusion Digital Power Software in
Revised oscillator manufacturer information from Epson to SiTime in
oscillator manufacturer information from Epson to SiTime on page
on page 44 referring to J55: "Note: This header is not installed on the SP605 as built."
Revised values for R50 and R216 in
information from Epson to SiTime on page
www.xilinx.com
Revision
Figure 1-23.
Table 1-24 and Table 1-25.
Table 1-11. Updated board connections for
1-12. Added note about FMC LPC J63 connector in
Appendix B, VITA 57.1 FMC LPC
Constraints.
Memory. Added note 1 to
Figure 1-12. Revised oscillator manufacturer
page 69.
18. VITA
Table 1-30.
Onboard Power Regulation.
Table 1-1. Revised
page 26. Deleted note
UG526 (v1.9) February 14, 2019