Mitsubishi Electric MELSEC iQ-R Series User Manual page 137

Address
Decimal (hexadecimal)
CH1 CH2 CH3 CH4
1810 to 1969 (712H to 7B1H)
1970 to 1999 (7B2H to 7CFH)
2000 2002 2004 2006
(7D0H) (7D2H) (7D4H) (7D6H)
2015 to 2031 (7DFH to 7EFH)
2032 (7F0H)
2033 to 2099 (7F1H to 833H)
2100 (834H)
2101 to 3749 (835H to EA5H)
*1 Item enabled by turning on and off 'Operating condition setting request' (Y9)
■Un\G3750 to Un\G89999
Address Address
(decimal) (hexadecimal)
3750 EA6H
3751 EA7H
3752 to 3759 EA8H to EAFH
3760 to 3919 EB0H to F4FH
3920 to 3999 F50H to F9FH
4000 to 4015 FA0H to FAFH
4016 to 4031 FB0H to FBFH
4032 to 4047 FC0H to FCFH
4048 to 4063 FD0H to FDFH
4064 to 4079 FE0H to FEFH
4080 to 4095 FF0H to FFFH
4096 to 4111 1000H to 100FH
4112 to 4127 1010H to 101FH
4128 to 4143 1020H to 102FH
4144 to 4159 1030H to 103FH
4160 to 4175 1040H to 104FH
4176 to 9999 1050H to 270FH
10000 to 89999 2710H to
15F8FH
*1 Item enabled by turning on and off 'Operating condition setting request' (Y9)
*2 [n] in the table indicates an interrupt setting number. (n = 1 to 16)
CH5 CH6 CH7
2008 2010 2012
(7D8H) (7DAH) (7DCH)
Name
Latest alarm code
Latest address of alarm history
System area
Alarm history No.1 to 16
System area
*2
Interrupt factor detection flag [n]
System area
*2
Interrupt factor mask [n]
System area
*2
Interrupt factor reset request [n]
System area
Interrupt factor generation setting [n]
System area
*2
Condition target setting [n]
System area
*2
Condition target channel setting [n]
System area
Wave data registry area
Name Default
value
CH8
Error history No.1 to 0
16
System area 
2014 CH 0
(7DEH) Synchronization
digital value
System area 
Output setting during 0
synchronous Error
System area 
Synchronization 0
status monitor
System area 
Default Data type
value
0 Monitor
0 Monitor
 
0 Monitor
 
0 Monitor
 
0 Control
 
0 Control
 
*2
0 Setting
 
0 Setting
 
0 Setting
 
0 Setting
Data Auto Enabled
*1
type refresh by Y9
 
Monitor
  
 
Control
  
 
Setting
  
 
Monitor
  
Auto Enabled by
*1
refresh Y9
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
APPENDICES
Appendix 3 Buffer Memory
A
135