Mitsubishi Electric MELSEC iQ-R Series User Manual page 145

Condition target channel setting [n]
Set a channel where an interrupt is detected.
Setting value
0
1
2
3
4
5
6
7
8
When a factor for the channel specification is set to 'Condition target setting [n]' (Un\G232 to Un\G247), an interrupt factor in
the channel set by this area is monitored. When a factor of the input signal (X) is set, the setting in this area is ignored. If a
value other than the above is set, a condition target setting range error (error code: 182H) occurs.
"n" and  indicate an interrupt setting number. (n = 1 to 16,  = 0 to F)
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Condition target channel setting [n]
Condition target channel setting [n]
(When the Q compatible mode
function is used)
■Setting range
For R60DA4, the setting range is from 0 to 4.
■Enabling the setting
Turn on and off 'Operating condition setting request' (Y9) to enable the setting.
■Default value
The default value is All CH specification (0) for all buffer memory areas.
Mode switching setting
Set a setting value for the mode to be switched.
Switching mode
Normal mode
Offset/gain setting mode
When a value other than the above is set, the mode switching is not executed and only the operating condition is changed.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Mode switching setting
Mode switching setting (When the Q compatible
mode function is used)
■Enabling the setting
Turn on 'Operating condition setting request' (Y9).
■After the mode is switched
When the mode is switched, this area is cleared to 0 and 'Operating condition setting completed flag' (X9) turns off.
After checking that 'Operating condition setting completed flag' (X9) is off, turn off 'Operating condition setting request' (Y9).
1 2 3 4 5
264 265 266 267 268
4160 4161 4162 4163 4164
Setting value
296
5260H
4441H
CH1 CH2
296, 297
158, 159
Setting content
All CH specification
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
6 7 8 9 10
269 270 271 272 273
4165 4166 4167 4168 4169
297
4441H
5260H
CH3 CH4 CH5
11 12 13 14 15
274 275 276 277 278
4170 4171 4172 4173 4174
CH6 CH7 CH8
APPENDICES
Appendix 3 Buffer Memory
16
279
4175
A
143