Mitsubishi Electric MELSEC iQ-R Series User Manual page 139

Latest address of alarm history
Among 'Alarm history No.' (Un\G3760 to Un\G3999), a buffer memory address which stores the latest alarm code is stored.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Latest address of alarm history
Latest address of alarm history (When the Q
compatible mode function is used)
Interrupt factor detection flag [n]
The detection status of the interrupt factor is stored.
Monitor value
0
1
When an interrupt factor occurs, an interrupt request is sent to the CPU module at the same time as 'Interrupt factor detection
flag [n]' (Un\G4 to Un\G19) is turned to Interrupt factor (1).
"n" indicates an interrupt setting number. (n = 1 to 16)
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Interrupt factor detection flag [n]
Interrupt factor detection flag [n]
(When the Q compatible mode
function is used)
Alert output upper limit flag
The upper limit alarm can be checked for each channel.
b15 b14 b13 b12 b11 b10 b9
0 0 0 0 0 0 0
(2)
(1) 0: Normal, 1: Alert alarm ON
(2) b4 to b15 of the R60DA4 and b8 to b15 of the R60DAV8 and R60DAI8 are fixed to 0.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Alert output upper limit flag
■Alert output upper limit flag status
• When the value is out of the range specified in the alert output upper limit value, Alert alarm ON (1) is stored in 'Alert output
upper limit flag' (Un\G36) corresponding to each channel.
• When an alert is detected in any channel where the D/A conversion and the alert output setting are enabled, 'Alert output
signal' (XE) also turns on.
■Clearing Alert output upper limit flag
Turn on and off 'Operating condition setting request' (Y9) or 'Alert output clear request' (YE).
CH1 CH2
3
3751
1 2 3 4 5
4 5 6 7 8
4000 4001 4002 4003 4004
b8 b7 b6 b5 b4 b3 b2
0 CH8 CH7 CH6 CH5 CH4 CH3
(1)
CH1 CH2
36
CH3 CH4 CH5
Description
No interrupt factor
Interrupt factor
6 7 8 9 10
9 10 11 12 13
4005 4006 4007 4008 4009
b1 b0
CH2 CH1
CH3 CH4 CH5
CH6 CH7 CH8
11 12 13 14 15
14 15 16 17 18
4010 4011 4012 4013 4014
CH6 CH7 CH8
APPENDICES
Appendix 3 Buffer Memory
16
19
4015
A
137