Pin Function Descriptions - Analog Devices ADSP-21367 Manual

ADSP-21367/ADSP-21368/ADSP-21369

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of
A = asynchronous, G = ground, I = input, O = output,
O/T = output three-state, P = power supply, S = synchronous,
(A/D) = active drive, (O/D) = open-drain, (pd) = pull-down
resistor, (pu) = pull-up resistor.
Table 5. Pin List
Name Type
ADDR O/T (pu)
23–0
1
DATA I/O (pu)
31–0
DAI _P I/O with programmable
20–1
2
pu
DPI _P I/O with programmable
14–1
2
pu
1
ACK I (pu)
RD O/T (pu)
WR O/T (pu)
SDRAS O/T (pu)
SDCAS O/T (pu)
Table
State During/
After Reset
(ID = 00x)
1
Pulled high/
driven low
Pulled high/
pulled high
Pulled high/
pulled high
Pulled high/
pulled high
1
Pulled high/
driven high
1
Pulled high/
driven high
1
Pulled high/
driven high
1
Pulled high/
driven high
Rev. D | Page 12 of 56 | November 2008
5: The ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces-
sors use extensive pin multiplexing to achieve a lower pin count.
For complete information on the multiplexing scheme, see the
ADSP-21368 SHARC Processor Hardware Reference, "System
Design" chapter.
Description
External Address. The processors output addresses for external memory and
peripherals on these pins.
External Data. Data pins can be multiplexed to support external memory
interface data (I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA
pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). When
configured using the IDP_PDAP_CTL register, IDP Channel 0 scans the DATA
pins for parallel input data.
Digital Applications Interface. These pins provide the physical interface to the
DAI SRU. The DAI SRU configuration registers define the combination of on-chip
audiocentric peripheral inputs or outputs connected to the pin, and to the pin's
output enable. The configuration registers then determines the exact behavior
of the pin. Any input or output signal present in the DAI SRU may be routed to
any of these pins. The DAI SRU provides the connection from the serial ports (8),
the SRC module, the S/PDIF module, input data ports (2), and the precision clock
generators (4), to the DAI_P20–1 pins. Pull-ups can be disabled via the
DAI_PIN_PULLUP register.
Digital Peripheral Interface. These pins provide the physical interface to the
DPI SRU. The DPI SRU configuration registers define the combination of on-chip
peripheral inputs or outputs connected to the pin and to the pin's output enable.
The configuration registers of these peripherals then determines the exact
behavior of the pin. Any input or output signal present in the DPI SRU may be
routed to any of these pins. The DPI SRU provides the connection from the timers
(3), SPIs (2), UARTs (2), flags (12) TWI (1), and general-purpose I/O (9) to the
DPI_P14–1 pins. The TWI output is an open-drain output—so the pins used for
2
I C data and clock should be connected to logic level 0. Pull-ups can be disabled
via the DPI_PIN_PULLUP register.
Memory Acknowledge. External devices can deassert ACK (low) to add wait
states to an external memory access. ACK is used by I/O devices, memory con-
trollers, or other peripherals to hold off completion of an external memory access.
External Port Read Enable. RD is asserted whenever the processors read a word
from external memory.
External Port Write Enable. WR is asserted when the processors write a word to
external memory.
SDRAM Row Address Strobe. Connect to SDRAM's RAS pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDRAM Column Address Select. Connect to SDRAM's CAS pin. In conjunction
with other SDRAM command pins, defines the operation for the SDRAM to
perform.
31–8