Analog Devices ADSP-21367 Manual page 45

JTAG Test Access Port and Emulation
Table 43. JTAG Test Access Port and Emulation
Parameter
Timing Requirements
t TCK Period
TCK
t TDI, TMS Setup Before TCK High
STAP
t TDI, TMS Hold After TCK High
HTAP
1
t System Inputs Setup Before TCK High
SSYS
1
t System Inputs Hold After TCK High
HSYS
t TRST Pulse Width
TRSTW
Switching Characteristics
t TDO Delay from TCK Low
DTDO
2
t System Outputs Delay After TCK Low
DSYS
1
System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.
2
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
ADSP-21367/ADSP-21368/ADSP-21369
t
TCK
t t
STAP HTAP
t
DTDO
t t
SSYS HSYS
t
DSYS
Figure 36. IEEE 1149.1 JTAG Test Access Port
Rev. D | Page 45 of 56 | November 2008
Min Max
t
CK
5
6
7
18
4t
CK
7
t ÷ 2 + 7
CK
Unit
ns
ns
ns
ns
ns
ns
ns
ns