Analog Devices ADSP-21367 Manual page 39

Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
Table 37. SRC, Serial Output Port
Parameter
Timing Requirements
1
t FS Setup Before SCLK Rising Edge
SRCSFS
1
t FS Hold After SCLK Rising Edge
SRCHFS
t Clock Width
SRCCLKW
t Clock Period
SRCCLK
Switching Characteristics
1
t Transmit Data Delay After SCLK Falling Edge
SRCTDD
1
t Transmit Data Hold After SCLK Falling Edge
SRCTDH
1
DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
t
- SRCCLKW
DAI_P20 1
(SCLK)
-
DAI_P20 1
(FS)
t
SRCTDD
-
DAI_P20 1
(SDATA)
t
SRCTDH
Figure 28. SRC Serial Output Port Timing
Rev. D | Page 39 of 56 | November 2008
ADSP-21367/ADSP-21368/ADSP-21369
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the
drive edge.
Min
4
5.5
(t × 8) ÷ 2 – 1
CCLK
t × 8
CCLK
1
SAMPLE EDGE
t
SRCCLK
t t
SRCSFS SRCHFS
Max Unit
ns
ns
ns
ns
9.9 ns
ns