Verter—Serial Input Port - Analog Devices ADSP-21367 Manual

ADSP-21367/ADSP-21368/ADSP-21369
Pulse-Width Modulation Generators
Table 35. PWM Timing
Parameter
Switching Characteristics
t PWM Output Pulse Width
PWMW
t PWM Output Period
PWMP
PWM
OUTPUTS
Sample Rate Converter—Serial Input Port
The SRC input signals SCLK, frame sync (FS), and SDATA are
routed from the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided in
DAI_P20–1 pins.
Table 36. SRC, Serial Input Port
Parameter
Timing Requirements
1
t FS Setup Before SCLK Rising Edge
SRCSFS
1
t FS Hold After SCLK Rising Edge
SRCHFS
1
t SDATA Setup Before SCLK Rising Edge
SRCSD
1
t SDATA Hold After SCLK Rising Edge
SRCHD
t Clock Width
SRCCLKW
t Clock Period
SRCCLK
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
t
PWMW
Figure 26. PWM Timing
Table 36 are valid at the
t
-
DAI_P20 1
SR CCLKW
(SCLK)
-
DAI_P20 1
(FS)
-
DAI_P20 1
(SDATA)
Figure 27. SRC Serial Input Port Timing
Rev. D | Page 38 of 56 | November 2008
Min
t – 2
PCLK
2 × t – 1.5
PCLK
t
PWMP
Min
4
5.5
4
5.5
(t
CCLK
t
CCLK
SAMPLE EDGE
t
SRCCLK
t t
SRCSFS
SRCHFS
t
t
SRCSD SRCHD
Max
16
(2 – 2) × t – 2
PCLK
16
(2 – 1) × t – 1.5
PCLK
Max
× 8) ÷ 2 – 1
× 8
Unit
ns
ns
Unit
ns
ns
ns
ns
ns
ns