Analog Devices ADSP-21367 Manual page 33

Table 30. Serial Ports—Internal Clock
Parameter
Timing Requirements
1
t FS Setup Before SCLK
SFSI
(Externally Generated FS in Either Transmit or Receive Mode)
1
t FS Hold After SCLK
HFSI
(Externally Generated FS in Either Transmit or Receive Mode)
1
t Receive Data Setup Before SCLK
SDRI
1
t Receive Data Hold After SCLK
HDRI
Switching Characteristics
2
t FS Delay After SCLK (Internally Generated FS in Transmit Mode)
DFSI
2
t FS Hold After SCLK (Internally Generated FS in Transmit Mode)
HOFSI
2
t FS Delay After SCLK (Internally Generated FS in Receive Mode)
DFSIR
2
t FS Hold After SCLK (Internally Generated FS in Receive Mode)
HOFSIR
2
t Transmit Data Delay After SCLK
DDTI
2
t Transmit Data Hold After SCLK
HDTI
3
t Transmit or Receive SCLK Width
SCLKIW
1
Referenced to the sample edge.
2
Referenced to drive edge.
3
Minimum SPORT divisor register value.
Table 31. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
1
t Data Enable from External Transmit SCLK
DDTEN
1
t Data Disable from External Transmit SCLK
DDTTE
1
t Data Enable from Internal Transmit SCLK
DDTIN
1
Referenced to drive edge.
Table 32. Serial Ports—External Late Frame Sync
Parameter
Switching Characteristics
1
t Data Delay from Late External Transmit FS or External Receive
DDTLFSE
FS with MCE = 1, MFD = 0
1
t Data Enable for MCE = 1, MFD = 0
DDTENFS
1
The t and t parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
DDTLFSE DDTENFS
ADSP-21367/ADSP-21368/ADSP-21369
Rev. D | Page 33 of 56 | November 2008
Min Max
7
2.5
7
2.5
4
–1.0
9.75
–1.0
3.25
–1.0
2 × t – 1.5 2 × t
PCLK
Min Max
2
10
–1
Min Max
7.75
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
+ 1.5 ns
PCLK
Unit
ns
ns
ns
Unit
ns
ns