Analog Devices ADSP-21367 Manual page 29

Memory Write
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
masters, accessing external memory space in asynchronous
Table 26. Memory Write
Parameter
Timing Requirements
t ACK Delay from Address, Selects
DAAK
t ACK Delay from WR Low
DSAK
Switching Characteristics
t Address, Selects to WR Deasserted
DAWH
t Address, Selects to WR Low
DAWL
t WR Pulse Width
WW
t Data Setup Before WR High
DDWH
t Address Hold After WR Deasserted
DWHA
t Data Hold After WR Deasserted
DWHD
t WR High to WR, RD Low
WWR
t Data Disable Before RD Low
DDWR
t WR Low to Data Enabled
WDE
W = (number of wait states specified in AMICTLx register) × t
H = (number of hold cycles specified in AMICTLx register) × t
1
ACK delay/setup: System must meet t
2
The falling edge of MSx is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
ADDRESS
MSx
WR
DATA
ACK
RD
1, 2
1, 3
2
2
, or t , for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t
DAAK DSAK
t
DAWH
t
DAWL
t
WDE
t
DSAK
t
DAAK
Figure 19. Memory Write
Rev. D | Page 29 of 56 | November 2008
ADSP-21367/ADSP-21368/ADSP-21369
access mode. Note that timing for ACK, DATA, RD, WR, and
strobe timing parameters only applies to asynchronous access
mode.
Min
t – 3.1+ W
SDCLK
t – 2.7
SDCLK
W – 1.3
t – 3.0+ W
SDCLK
H + 0.15
H + 0.02
t – 1.5+ H
SDCLK
2t – 4.11
SDCLK
t – 3.5
SDCLK
.
SDCLK
.
SDCLK
t
WW
t
DDWH
Max
t – 9.7 + W
SDCLK
W – 4.9
or t .
DAAK DSAK
t
DWHA
t
WWR
t
DDWR
t
DWHD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns