Analog Devices ADSP-21367 Manual page 40

ADSP-21367/ADSP-21368/ADSP-21369
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
2
left justified, I S, or right justified with word widths of 16, 18, 20,
or 24 bits. The following sections provide timing for the
transmitter.
-
DAI_P20 1
LRCLK
-
DAI_P20 1
SCLK
LSB
-
DAI_P20 1
SDATA
Figure 30 shows the default I
for the left channel and high for the right channel. Data is valid
on the rising edge of SCLK. The MSB is left-justified to an
LRCLK transition but with a single SCLK period delay.
-
DAI_P20 1
LRCLK
-
DAI_P20 1
SCLK
-
DAI_P20 1
MSB
SDATA
Figure 31 shows the left-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition with no MSB delay.
-
DAI_P20 1
LRCLK
-
DAI_P20 1
SCLK
MSB MSB-1
-
DAI_P20 1
SDATA
LEFT CHANNEL
MSB-1 MSB-2
MSB
Figure 29. Right-Justified Mode
2
S-justified mode. LRCLK is low
LEFT CHANNEL
MSB-1 MSB-2 LSB+2 LSB+1 LSB
LEFT CHANNEL
MSB-2 LSB+2 LSB+1 LSB
Figure 31. Left-Justified Mode
Rev. D | Page 40 of 56 | November 2008
S/PDIF Transmitter—Serial Input Waveforms
Figure 29 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data is right-
justified to the next LRCLK transition.
LSB+2 LSB+1 LSB
RIGHT CHANNEL
MSB MSB-1
2
Figure 30. I S-Justified Mode
MSB MSB-1 MSB-2
RIGHT CHANNEL
MSB MSB-1 MSB-2
MSB-2 LSB+2 LSB+1 LSB
RIGHT CHANNEL
LS B+2 LSB+1 LSB
LSB+2 LSB+1 LSB
MSB
MSB MSB+1