Analog Devices ADSP-21367 Manual page 41

S/PDIF Transmitter Input Data Timing
The timing requirements for the input port are given in
Table 38. Input signals SCLK, frame sync (FS), and SDATA are
routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 38. S/PDIF Transmitter Input Data Timing
Parameter
Timing Requirements
1
t FS Setup Before SCLK Rising Edge
SISFS
1
t FS Hold After SCLK Rising Edge
SIHFS
1
t SData Setup Before SCLK Rising Edge
SISD
1
t SData Hold After SCLK Rising Edge
SIHD
t Clock Width
SISCLKW
t Clock Period
SISCLK
t Transmit Clock Width
SITXCLKW
t Transmit Clock Period
SITXCLK
1
DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This TxCLK
input is divided down to generate the biphase clock.
Table 39. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
TxCLK Frequency for TxCLK = 384 × FS
TxCLK Frequency for TxCLK = 256 × FS
Frame Rate
SAMPLE EDGE
t
SITXCLKW
-
DAI_P20 1
(TXCLK)
-
DAI_P20 1
(SCLK)
-
DAI_P20 1
(FS)
-
DAI_P20 1
(SDATA)
Figure 32. S/PDIF Transmitter Input Timing
Rev. D | Page 41 of 56 | November 2008
ADSP-21367/ADSP-21368/ADSP-21369
Min
3
3
3
3
36
80
9
20
t
SITXCLK
t
SISCLKW
t
SISFS
t
SISD
Min
Max
t
SIHFS
t
SIHD
Max
73.8
49.2
192.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
MHz
kHz