Analog Devices ADSP-21367 Manual page 26

ADSP-21367/ADSP-21368/ADSP-21369
SDRAM Interface Timing (166 MHz SDCLK)
The 166 MHz access speed is for a single processor. When mul-
tiple ADSP-21368 processors are connected in a shared memory
system, the access speed is 100 MHz.
Table 23. SDRAM Interface Timing
Parameter
Timing Requirements
t DATA Setup Before SDCLK
SSDAT
t DATA Hold After SDCLK
HSDAT
Switching Characteristics
t SDCLK Period
SDCLK
t SDCLK Width High
SDCLKH
t SDCLK Width Low
SDCLKL
t Command, ADDR, Data Delay After SDCLK
DCAD
t Command, ADDR, Data Hold After SDCLK
HCAD
t Data Disable After SDCLK
DSDAT
t Data Enable After SDCLK
ENSDAT
1
For f = 400 MHz (SDCLK ratio = 1:2.5).
CCLK
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.
SDCLK
DATA (IN)
DATA(OUT)
CMND ADDR
(OUT)
1
Min
500
1.23
7.14
3
3
2
2
1.2
1.3
t
SSDAT
t
DCAD
Figure 16. SDRAM Interface Timing
Rev. D | Page 26 of 56 | November 2008
The processor needs to be programmed in t
mode when operated at 350 MHz.
350 MHz
Max
4.8
5.3
t
SDCLK
t
SDCLKL
t
HSDAT
t
DCAD
t
ENSDAT
t
HCAD
= 2.5 × t
SDCLK
All Other Speed Grades
Min Max
500
1.23
6.0
2.6
2.6
4.8
1.2
5.3
1.3
t
SDCLKH
t
DSDAT
t
HCAD
CCLK
Unit
Unit
ps
ns
ns
ns
ns
ns
ns
ns
ns