Analog Devices ADSP-21367 Manual page 28

ADSP-21367/ADSP-21368/ADSP-21369
Memory Read
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the processors are the bus
master accessing external memory space in asynchronous access
mode. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 25. Memory Read
Parameter
Timing Requirements
t Address, Selects Delay to Data Valid
DAD
t RD Low to Data Valid
DRLD
t Data Setup to RD High
SDS
t Data Hold from RD High
HDRH
t ACK Delay from Address, Selects
DAAK
t ACK Delay from RD Low
DSAK
Switching Characteristics
t Address Selects Hold After RD High
DRHA
t Address Selects to RD Low
DARL
t RD Pulse Width
RW
t RD High to WR, RD Low
RWR
W = (number of wait states specified in AMICTLx register) × t
HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × t
IC = (number of idle cycles specified in AMICTLx register) × t
H = (number of hold cycles specified in AMICTLx register) × t
1
The falling edge of MSx is referenced.
2
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
3
Data hold: User must meet t or t
HDA
4
ACK delay/setup: User must meet t
ADDRESS
MSx
RD
DATA
ACK
WR
1
2, 3
1, 4
4
1
in asynchronous access mode. See
HDRH
, or t , for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet t
DAAK DSAK
t
DARL
t
DAD
t
DSAK
t
DAAK
Figure 18. Memory Read
Rev. D | Page 28 of 56 | November 2008
Min
2.5
0
RH + 0.20
t – 3.3
SDCLK
W – 1.4
HI + t – 0.8
SDCLK
.
SDCLK
SDCLK
.
SDCLK
.
SDCLK
Test Conditions on Page 46 for the calculation of hold times given capacitive and dc loads.
t
RW
t
DRLD
Max
W + t –5.12
SDCLK
W – 3.2
t –9.5 + W
SDCLK
W – 7.0
DAAK
t
DRHA
t
SDS
t
HDRH
t
RWR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
or t .
DSAK