Analog Devices ADSP-21367 Manual page 35

DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
-
DAI_P20 1
(SCLK)
t
DFSIR
t
HOFSIR
-
DAI_P20 1
(FS)
-
DAI_P20 1
(DATA CHANNEL A/B)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
-
DAI_P20 1
(SCLK)
t
DFSI
t
HOFSI
-
DAI_P20 1
(FS)
t
HDTI
DAI_P20 - 1
(DATA CHANNEL A/B)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
-
DAI_P20 1
SCLK (EXT)
-
DAI_P20 1
(DATA CHANNEL A/B)
-
DAI_P20 1
SCLK (INT)
-
DAI_P20 1
(DATA CHANNEL A/B)
SAMPLE EDGE
t
SCLKIW
t
t
HFSI
SFSI
t t
SDRI HDRI
SAMPLE EDGE
t
SCLKIW
t
t HFSI
SFSI
t
DDTI
DRIVE EDGE
t
DDTEN
DRIVE EDGE
t
DDTIN
Figure 23. Serial Ports
Rev. D | Page 35 of 56 | November 2008
ADSP-21367/ADSP-21368/ADSP-21369
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
-
DAI_P20 1
(SCLK)
t
DFSE
t
HOFSE
-
DAI_P20 1
(FS)
-
DAI_P20 1
(DATA CHANNEL A/B)
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE
-
DAI_P20 1
(SCLK)
t
DFSE
t
HOFSE
-
DAI_P20 1
(FS)
t
HDTE
DAI_P20 - 1
(DATA CHANNEL A/B)
DRIVE EDGE
SCLK
t
DDTTE
SAMPLE EDGE
t
SCLKW
t
HFSE
t
SFSE
t
t
HDRE
SDRE
SAMPLE EDGE
t
SCLKW
t t
SFSE HFSE
t
DDTE