Analog Devices ADSP-21367 Manual page 44

ADSP-21367/ADSP-21368/ADSP-21369
SPI Interface—Slave
Table 42. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Timing Requirements
t Serial Clock Cycle
SPICLKS
t Serial Clock High Period
SPICHS
t Serial Clock Low Period
SPICLS
t SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1
SDSCO
t Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
HDS
t Data Input Valid to SPICLK Edge (Data Input Setup Time)
SSPIDS
t SPICLK Last Sampling Edge to Data Input Not Valid
HSPIDS
t SPIDS Deassertion Pulse Width (CPHASE = 0)
SDPPW
Switching Characteristics
t SPIDS Assertion to Data Out Active
DSOE
1
t SPIDS Assertion to Data Out Active (SPI2)
DSOE
t SPIDS Deassertion to Data High Impedance
DSDHI
1
t SPIDS Deassertion to Data High Impedance (SPI2)
DSDHI
t SPICLK Edge to Data Out Valid (Data Out Delay Time)
DDSPIDS
t SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
HDSPIDS
t SPIDS Assertion to Data Out Valid (CPHASE = 0)
DSOV
1
The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-21368 SHARC Processor Hardware
Reference, "Serial Peripheral Interface Port" chapter.
SPIDS
(INPUT)
t
S P I C H S
SPICLK
(CP = 0)
(INPUT)
t
S D S C O
SPICLK
(CP = 1)
(INPUT)
t
D S O E
MISO
(OUTPUT)
t
CPHASE = 1
S S P I D S
MOSI
(INPUT)
t
D S O V
t
D S O E
MISO
(OUTPUT)
CPHASE = 0
MOSI
(INPUT)
t
S P I C L S
t
S P I C L S
t
S P I C H S
t
D D S P I D S
MSB
MSB VALID
t
D D S P I D S
MSB
MSB VALID
Figure 35. SPI Slave Timing
Rev. D | Page 44 of 56 | November 2008
t
S P I C L K S
t
H D S
t
D D S P I D S
LSB
t
H S P ID S
t
S S P I D S
LSB VALID
t
H D S P ID S
LSB
t
H S P ID S
t
S S P I D S
LSB VALID
Min Max
4 × t – 2
PCLK
2 × t – 2
PCLK
2 × t – 2
PCLK
2 × t
PCLK
2 × t
PCLK
2
2
2 × t
PCLK
0 6.8
0 8
0 6.8
0 8.6
9.5
2 × t
PCLK
5 × t
PCLK
t
S D P P W
t
D S D H I
t
H D S P ID S
t
D S D H I
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns