Analog Devices ADSP-21367 Manual page 27

SDRAM Interface Enable/Disable Timing (166 MHz SDCLK)
Table 24. SDRAM Interface Enable/Disable Timing
Parameter
Switching Characteristics
t Command Disable After CLKIN Rise
DSDC
t Command Enable After CLKIN Rise
ENSDC
t SDCLK Disable After CLKIN Rise
DSDCC
t SDCLK Enable After CLKIN Rise
ENSDCC
t Address Disable After CLKIN Rise
DSDCA
t Address Enable After CLKIN Rise
ENSDCA
1
For f = 400 MHz (SDCLK ratio = 1:2.5).
CCLK
1
CLKIN
COMMAND
SDCLK
ADDR
COMMAND
SDCLK
ADDR
Figure 17. SDRAM Interface Enable/Disable Timing
Rev. D | Page 27 of 56 | November 2008
ADSP-21367/ADSP-21368/ADSP-21369
Min
4.0
3.8
2 × t
PCLK
t
DSDC
t
DSDCC
t
DSDCA
t
ENSDC
t
ENSDCC
t
ENSDCA
Max
2 × t + 3
PCLK
8.5
9.2
– 4 4 × t
PCLK
Unit
ns
ns
ns
ns
ns
ns