Package Information; Esd Caution; Maximum Power Dissipation; Absolute Maximum Ratings - Analog Devices ADSP-21367 Manual

PACKAGE INFORMATION

The information presented in
the package branding for the ADSP-21367/ADSP-21368/
ADSP-21369 processors. For a complete listing of product avail-
ability, see Ordering Guide on Page
a
ADSP-2136x
vvvvvv.x n.n
#yyww country_of_origin
S
Figure 3. Typical Package Brand
Table 9. Package Brand Information
Brand Key Field Description
t Temperature Range
pp Package Type
Z RoHS Compliant Option
cc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
# RoHS Compliant Designation
yyww Date Code

ESD CAUTION

ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.

MAXIMUM POWER DISSIPATION

See Estimating Power Dissipation for ADSP-21368 SHARC Pro-
cessors (EE-299) for detailed thermal and power information
regarding maximum power dissipation. For information on
package thermal specifications, see
Page 48.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 3 provides details about
55.
tppZ-cc
Thermal Characteristics on
Table 10 may cause perma-
Rev. D | Page 17 of 56 | November 2008
ADSP-21367/ADSP-21368/ADSP-21369
Table 10. Absolute Maximum Ratings
Parameter
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (A
External (I/O) Supply Voltage (V
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Junction Temperature Under Bias

TIMING SPECIFICATIONS

The processor's internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor's internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins (see
To determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).
The processor's internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor's internal clock.
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control shown in
and Table 12.
In Table 11, CCLK is defined as:
f = (2 × PLLM × f
CCLK INPUT
where:
f = CCLK frequency
CCLK
PLLM = Multiplier value programmed
PLLN = Divider value programmed
Table 11. ADSP-21368 Clock Generation Operation
Timing
Requirements Description
CLKIN Input Clock
CCLK Core Clock
Note the definitions of various clock periods shown in
which are a function of CLKIN and the appropriate ratio con-
trol shown in Table 11.
Rating
) –0.3 V to +1.5 V
DDINT
) –0.3 V to +1.5 V
VDD
) –0.3 V to +4.6 V
DDEXT
–0.5 V to +3.8 V
–0.5 V to V
+ 0.5 V
DDEXT
200 pF
–65°C to +150°C
125°C
Table 8 on Page
Table 11
) ÷ (2 × PLLN)
Calculation
1/t
CK
1/t
CCLK
Table 12
15).