Analog Devices ADSP-21367 Manual page 13

Table 5. Pin List
Name Type
1
SDWE O/T (pu)
1
SDCKE O/T (pu)
1
SDA10 O/T (pu)
SDCLK0 O/T
SDCLK1 O/T
1
MS O/T (pu)
0–1
FLAG[0]/IRQ0 I/O
FLAG[1]/IRQ1 I/O
FLAG[2]/IRQ2/ I/O with programmable
MS pu (for MS mode)
2
FLAG[3]/TIMEXP/ I/O with programmable
MS pu (for MS mode)
3
TDI I (pu)
TDO O/T
TMS I (pu)
TCK I
TRST I (pu)
EMU O/T (pu)
ADSP-21367/ADSP-21368/ADSP-21369
State During/
After Reset
(ID = 00x) Description
Pulled high/ SDRAM Write Enable. Connect to SDRAM's WE or W buffer pin.
driven high
Pulled high/ SDRAM Clock Enable. Connect to SDRAM's CKE pin. Enables and disables the
driven high CLK signal. For details, see the data sheet supplied with the SDRAM device.
Pulled high/ SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-
driven low
SDRAM accesses. This pin replaces the DSP's A10 pin only during SDRAM
accesses.
High-Z/driving SDRAM Clock Output 0. Clock driver for this pin differs from all other clock
drivers. See
SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with
multiple SDRAM devices, handles the increased clock load requirements, elimi-
nating need of off-chip clock buffers. Either SDCLK1 or both SDCLKx pins can be
three-stated. Clock driver for this pin differs from all other clock drivers. See
Figure 38 on Page
The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available
on the LQFP_EP package.
Pulled high/ Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the
driven high corresponding banks of external memory. The MS
address lines that change at the same time as the other address lines. When no
external memory access is occurring, the MS
however, when a conditional memory access instruction is executed, whether or
not the condition is true.
The MS pin can be used in EPORT/FLASH boot mode. See the hardware reference
1
for more information.
High-Z/high-Z FLAG0/Interrupt Request 0.
High-Z/high-Z FLAG1/Interrupt Request 1.
High-Z/high-Z FLAG2/Interrupt Request 2/Memory Select 2.
High-Z/high-Z FLAG3/Timer Expired/Memory Select 3.
Test Data Input (JTAG). Provides serial data for the boundary scan logic.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Mode Select (JTAG). Used to control the test state machine.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up, or held low for proper operation of the processor
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed
low) after power-up or held low for proper operation of the processor.
Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/
ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target
board connectors only.
Rev. D | Page 13 of 56 | November 2008
Figure 38 on Page 46.
46.
lines are decoded memory
3-0
lines are inactive; they are active,
3-0