Analog Devices ADSP-21367 Manual page 30

Sharc processors
Hide thumbs Also See for ADSP-21367:
Table of Contents

Advertisement

ADSP-21367/ADSP-21368/ADSP-21369
Asynchronous Memory Interface (AMI) Enable/Disable
Use these specifications for passing bus mastership between
ADSP-21368 processors (BRx).
Table 27. AMI Enable/Disable
Parameter
Switching Characteristics
t
Address/Control Enable After Clock Rise
ENAMIAC
t
Data Enable After Clock Rise
ENAMID
t
Address/Control Disable After Clock Rise
DISAMIAC
t
Data Disable After Clock Rise
DISAMID
CLKIN
ADDR, WR, RD,
MS1 - 0, DATA
ADDR, WR, RD,
MS1 - 0, DATA
Figure 20. AMI Enable/Disable
Rev. D | Page 30 of 56 | November 2008
Min
4
t
+ 4
SDCLK
t
DISAMIAC
t
DISAMID
t
ENAMIAC
t
ENAMID
Max
Unit
ns
ns
8.7
ns
0
ns

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the ADSP-21367 and is the answer not in the manual?

Questions and answers

This manual is also suitable for:

Adsp-21368Adsp-21369

Table of Contents