Analog Devices ADSP-21367 Manual page 18

ADSP-21367/ADSP-21368/ADSP-21369
Table 12. Clock Periods
Timing
Requirements Description
t CLKIN Clock Period
CK
t (Processor) Core Clock Period
CCLK
t (Peripheral) Clock Period = 2 × t
PCLK
t Serial Port Clock Period = (t
SCLK
t SDRAM Clock Period = (t
SDCLK
t SPI Clock Period = (t
SPICLK
1
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV
bits in DIVx register)
SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register
setting)
SPICLK = SPI clock
SDR = SDRAM-to-core clock ratio (values determined by Bits 20–18 of the
PMCTL register)
Figure 4 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-21368 SHARC Processor Hard-
ware Reference and Managing the Core PLL on Third-
Generation SHARC Processors (EE-290).
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
CLKIN
CLKIN
DIVIDER
XTAL
BUF
PMCTL
DELAY OF
RESET
4096 CLKIN
CYCLES
1
CCLK
) × SR
CCLK
) × SDR
CCLK
) × SPIR
CCLK
PLL
PLLI
CLK
LOOP
VCO
FILTER
PLL
MULTIPLIER
CLK_CFGx/PMCTL
CLKOUT
RESETOUT
Figure 4. Core Clock and System Clock Relationship to CLKIN
Rev. D | Page 18 of 56 | November 2008
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 39 on Page 46 under
ence levels.
Note that in the user application, the PLL multiplier value
should be selected in such a way that the VCO frequency never
exceeds f specified in
VCO
lated as follows:
= 2 × PLLM × f
f
VCO INPUT
where:
f is the VCO frequency
VCO
PLLM is the multiplier value programmed
f is the input frequency to the PLL in MHz.
INPUT
f = CLKIN when the input divider is disabled
INPUT
= CLKIN ÷ 2 when the input divider is enabled
f
INPUT
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
PMCTL
CCLK
SDRAM
PLL
DIVIDER
DIVIDER
DIVIDE
CLK_CFGx/
PMCTL
PMCTL
Test Conditions for voltage refer-
Table 14. The VCO frequency is calcu-
CLK_CFGx/
PMCTL
SDCLK
PCLK
BY 2
PCLK
CCLK
RESETOUT/
BUF
CLKOUT
CORERST