Analog Devices ADSP-21367 Manual page 19

Power-Up Sequencing
The timing requirements for processor start-up are given in
Table 13. Note that during power-up, a leakage current of
approximately 200μA may be observed on the RESET pin if it is
Table 13. Power-Up Sequencing Timing Requirements (Processor Start-up)
Parameter
Timing Requirements
t RESET Low Before V
RSTVDD
t V
IVDDEVDD DDINT
1
t CLKIN Valid After V
CLKVDD
t CLKIN Valid Before RESET Deasserted
CLKRST
t PLL Control Setup Before RESET Deasserted
PLLRST
Switching Characteristic
t Core Reset Deasserted After RESET Deasserted
CORERST
1
Valid V /V assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
DDINT DDEXT
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate
default states at all I/O pins.
4
The 4096 cycle count depends on t
maximum.
CLK_CFG1-0
RESETOUT
(MULTIPLEXED WITH CLKOUT)
/V On
DDINT DDEXT
On Before V
DDEXT
/V Valid
DDINT DDEXT
specification in Table 15. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles
srst
RESET
t
RSTVDD
V
DDINT
V
DDEXT
CLKIN
Figure 5. Power-Up Sequencing
Rev. D | Page 19 of 56 | November 2008
ADSP-21367/ADSP-21368/ADSP-21369
driven low before power up is complete. This leakage current
results from the weak internal pull-up resistor on this pin being
enabled during power-up.
Min
0
–50
0
2
10
20
4096t + 2 t
CK
t
IVDDEVDD
t
CLKVDD
t
CLKRST
t
CORERST
t
PLLRST
Max Unit
ns
+200 ms
200 ms
μs
μs
3, 4
CCLK