Analog Devices ADSP-21367 Manual page 21

Reset
Table 15. Reset
Parameter
Timing Requirements
1
t RESET Pulse Width Low
WRST
t RESET Setup Before CLKIN Low
SRST
Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
1
V and CLKIN (not including start-up time of external clock oscillator).
DD
CLKIN
RESET
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.
Table 16. Interrupts
Parameter
Timing Requirement
t IRQx Pulse Width
IPW
Min
4t
8
t
WRST
Figure 8. Reset
DAI_P20 - 1
DPI_14 - 1
FLAG2 - 0
(IRQ2 - 0)
t
IPW
Figure 9. Interrupts
Rev. D | Page 21 of 56 | November 2008
ADSP-21367/ADSP-21368/ADSP-21369
Max
CK
t
SRST
Min
2 × t +2
PCLK
Unit
ns
ns
Max Unit
ns