Analog Devices ADSP-21367 Manual page 14

ADSP-21367/ADSP-21368/ADSP-21369
Table 5. Pin List
Name Type
CLK_CFG I
1–0
BOOT_CFG I
1–0
RESET I
XTAL O
CLKIN I
RESETOUT/ O/T
CLKOUT
1
BR I/O (pu)
4–1
ID I (pd)
2–0
1
RPBA I (pu)
1
The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID
2
Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
State During/
After Reset
(ID = 00x) Description
Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See
Table 8 for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL
multiplier and divider in the PMCTL register at any time after the core comes out
of reset.
Boot Configuration Select. These pins select the boot mode for the processor.
The BOOT_CFG pins must be valid before reset is asserted. See
description of the boot modes.
Processor Reset. Resets the processor to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input
must be asserted (low) at power-up.
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
Local Clock In. Used with XTAL. CLKIN is the processor's clock input. It configures
the processors to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving
XTAL unconnected configures the processor to use an external clock such as an
external clock oscillator. CLKIN may not be halted, changed, or operated below
the specified frequency.
Driven low/ Reset Out/Local Clock Out. Reset out provides a 4096 cycle delay that allows
driven high the PLL to lock. This pin can also be configured as a CLKOUT signal to clock
synchronous peripherals and memory. The functionality can be switched
between the PLL output clock and reset out by setting Bit 12 of the PMCTL
register. The default is reset out.
Pulled high/ External Bus Request. Used by the ADSP-21368 processor to arbitrate for bus
pulled high mastership. A processor only drives its own BR
of its ID2-0 inputs) and monitors all others. In a system with less than four pro-
cessors, the unused BR
must not be tied high or low because it is an output.
Processor ID. Determines which bus request (BR
processor. ID = 001 corresponds to BR
ID = 000 or 001 in single-processor systems. These lines are a system configura-
tion selection that should be hardwired or only changed at reset. ID = 101,110,
and 111 are reserved.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority
for the ADSP-21368 external bus arbitration is selected. When RPBA is low, fixed
priority is selected. This signal is a system configuration selection which must be
set to the same value on every processor in the system.
Rev. D | Page 14 of 56 | November 2008
line (corresponding to the value
x
pins should be tied high; the processor's own BR
x
) is used by the ADSP-21368
4–1
ID = 010 corresponds to BR
1,
Table 7 for a
line
x
, and so on. Use
2
= 00x
2–0