A9 Nvram - Agilent Technologies 35670A Service Manual

Address Latch
Data Buffer
Address Decode
Level Shift
SRAM Array
A9 NVRAM Block Diagram
Circuit Descriptions

A9 NVRAM

A9 NVRAM
The optional A9 NVRAM assembly provides the A7 CPU assembly with additional
nonvolatile RAM.
Holds the address from the processor address bus. This circuit latches the address when an
address strobe occurs (BBASn goes low).
Buffers the processor data bus.
Enables one of the eight battery-backed static RAM chips in the SRAM Array.
Disables the SRAM Array during power-up and power down, when the A7 CPU assembly's
processor is externally reset, and when +5 volts on the A8 Memory assembly is too low.
Contains eight battery-backed static RAM chips.
8-32
Agilent 35670A