Agilent Technologies 35670A Service Manual page 309

DC Offset DAC
Anti-Alias Filter Bypass Bypasses all filters.
100 kHz Anti-Alias
Filter
50 kHz Anti-Alias Filter Provides alias protection up to 50 kHz for two channel measurements.
A-Weight Filter
Analog Switch
Half Range and
Differential Overload
Detectors
IIC (Inter-IC) Interface Contains 32 ports and connects the A1 Input assembly to the serial IIC bus. The A7 CPU
Agilent 35670A
Compensates for any dc offset added to the input signal due to circuitry in the signal path. The
required dc offset is calculated during the analyzer's calibration routine and is added to the
input signal in 0.345 mV increments by varying the dc offset at the inverting input of the +2 dB
Amplifier (see "Calibration Routine Description" in chapter 10).
Provides alias protection up to 100 kHz for single channel measurements. Only the channel 1
input path has a 100 kHz Anti-Alias Filter.
Provides additional filtering in the 50 kHz anti-alias filter path for acoustic measurements.
Selects one of four possible signals in the channel 1 input path to send to the ADC — the signal
from the Anti-Alias Filter Bypass, 100 kHz Anti-Alias Filter, 50 kHz Anti-Alias Filter, or
A-Weight Filter. In the channel 2 input path, the Analog Switch selects one of three possible
signals to send to the ADC — the signal from the Anti-Alias Filter Bypass, 50 kHz Anti-Alias
Filter, or A-Weight Filter.
Sense the signal at the anti-alias filters. When a detector detects a half-range or overload
condition, a digital low is sent to the IIC Interface by the detector. The half-range detector also
sends a control signal to the A13 Primary Keypad assembly when a half-range condition
occurs.
assembly uses the IIC bus to configure the input circuits. When a common mode or differential
overload occurs, the IIC Interface forces SINTn low to interrupt the CPU assembly. The CPU
assembly then reads the IIC Interface to determine the type of interrupt and the channel it
occurred on. During up/down autoranging, the A7 CPU queries the A1 Input assembly for half
range status. For a description of the IIC bus, see the description of the IIC Controller for the
"A7 CPU" later in this chapter.
Circuit Descriptions
A1 Input
8-7