Agilent Technologies 35670A Service Manual page 327

MPU (Microprocessor) Controls the processor address bus and the buffered processor data bus. At power-up, this
Monitor ROM
DSP and Floating Point
Math Co-processor
Interrupt Handler
Data Transfer Handler
Clock Circuits
Agilent 35670A
A7 CPU
The A7 CPU assembly controls the entire analyzer. It performs multiple tasks, such
as:
Initiating the power-up sequence and calibration routines
•
Capturing front panel keystrokes
•
Configuring the measurement hardware
•
Processing input data from the A6 Digital assembly
•
Controlling the A101 Display assembly
•
Monitoring the hardware for faults or overloads
•
Running the self tests
•
Handling all data transfers for the fast bus, rear bus, and A100 Disk Drive assembly
•
circuit initializes the analyzer from the information stored in the Monitor ROM. This circuit
also processes interrupts from the Interrupt Handler and synchronizes data transfers on the
processor data bus with the Data Transfer Handler. The MPU also has access to
battery-backed-up SRAM on the A8 Memory assembly. This allows the CPU assembly to
store and update information such as the analyzer's address, default disk, and peripheral
addresses.
Stores the information used by the MPU to initialize the analyzer.
Relieve the MPU of math intensive-tasks by supplying the computational power needed for
accurate, high-speed signal processing operations — for example, windowing and Fast Fourier
Transform (FFT) for the analyzer's narrow-band zoom mode. The DSP Co-processor is a high
speed (40 MHz) math co-processor that performs complex mathematical operations. The
Floating Point Math Co-processor performs floating point mathematical operations. The DSP
Co-processor and Floating Point Math Co-processor work as slave co-processors to the MPU
and the DSP Co-processor has its own RAM. This arrangement leaves the MPU free to
perform other functions while the DSP Co-processor and Floating Point Math Co-processor
perform math-intensive operations.
Processes interrupts for the MPU. The Interrupt Handler sets the interrupt priority level and
returns an interrupt acknowledge to the circuit that generated the interrupt. If the MFP
controller causes an interrupt, the MPU reads a status byte from the MFP controller to
determine the circuit that caused the interrupt.
Synchronizes data transfers in the analyzer with the MPU. When a data transfer occurs, the
Data Transfer Handler notifies the MPU when the transfer is complete.
Provide the clocks for the CPU assembly and the A8 Memory assembly.
Circuit Descriptions
A7 CPU
8-25