Read Cycle - Motorola MC68020 User Manual

5.3.1 Read Cycle

During a read cycle, the processor receives data from a memory, coprocessor, or
peripheral device. If the instruction specifies a long-word operation, the MC68020/EC020
attempts to read four bytes at once. For a word operation, it attempts to read two bytes at
once and for a byte operation, one byte. For some operations, the processor requests a
three-byte transfer. The processor properly positions each byte internally. The section of
the data bus from which each byte is read depends on the operand size, A1–A0, and the
port size. Refer to 5.2.1 Dynamic Bus Sizing and 5.2.2 Misaligned Operands for more
information on dynamic bus sizing and misaligned operands.
Figure 5-19 is a flowchart of a long-word read cycle. Figure 5-20 is a flowchart of a byte
read cycle. Figures 5-21–5-23 are read cycle timing diagrams in terms of clock periods.
Figure 5-21 corresponds to byte and word read cycles from a 32-bit port. Figure 5-22
corresponds to a long-word read cycle from an 8-bit port. Figure 5-23 also applies to a
long-word read cycle, but from 16- and 32-bit ports.
ADDRESS DEVICE
* 1) ASSERT ECS/OCS FOR ONE-HALF CLOCK
2) SET R/W TO READ
** 3) DRIVE ADDRESS ON A31–A0
4) DRIVE FUNCTION CODE ON FC2–FC0
5) DRIVE SIZ1, SIZ0 (FOUR BYTES)
6) ASSERT AS
7) ASSERT DS
* 8) ASSERT DBEN
1) LATCH DATA
2) NEGATE AS AND DS
* 3) NEGATE DBEN
START NEXT CYCLE
* This step does not apply to the MC68EC020.
For the MC68EC020, A23–A0.
5-26
PROCESSOR
ACQUIRE DATA
Figure 5-19. Long-Word Read Cycle Flowchart
M68020 USER'S MANUAL
EXTERNAL DEVICE
PRESENT DATA
1) DECODE ADDRESS
2) PLACE DATA ON D31–D0
3) ASSERT DSACK1/DSACK0
TERMINATE CYCLE
1) REMOVE DATA FROM D31–D0
2) NEGATE DSACK1/DSACK0
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