The Gpio Tab - Intel Cyclone 10 GX FPGA User Manual

5 Board Test System
UG-20105 | 2017.12.18
Table 19. MAX 10 Registers
MAX 10 Register Values
Configure
PSO
PSR
PSS
JTAG Chain
The JTAG chain shows all the devices currently in the JTAG chain.
Note: System MAX and FPGA should all be present in the JTAG chain when running BTS GUI.

5.3.3 The GPIO Tab

The GPIO tab allows you to interact with all the general purpose user I/O components
on your board. You can read DIP switch settings, turn LEDs on or off and detect push
button presses.
Figure 13. The GPIO Tab
The following sections describe the controls on the GPIO tab.
Resets the system and reloads the FPGA with a design from the CFI flash memory
based on the other Intel MAX 10 register values. It works only in FPP mode.
Sets the Intel MAX 10 PSO register.
Sets the Intel MAX 10 PSR register. Allows PSR to determine the page of flash
memory to use for FPGA reconfiguration. The numerical values in the list
corresponds to the page of flash memory to load during the FPGA configuration.
Displays the Intel MAX 10 PSS register value. Allows the PSS to determine the
page of flash memory to use for FPGA reconfiguration.
Intel
Description
® ®
Cyclone 10 GX FPGA Development Kit User Guide
45