The Gpio Tab - Intel Stratix 10 GX User Manual

6 Board Test System
• Board Name: Indicates the official name of the board given by the BTS.
• Board P/N: Indicates the part number of the board.
• Serial Number: Indicates the serial number of the board.
• Board Revision: Indicates the revision of the board.
• MAC: Indicates the MAC address of the board.
System-MAX Control
The MAX V register control allows you to view and change the current MAX V register
values as described in the table below. Change to the register values with the GUI
take effect immediately.
Table 24. MAX V Registers
MAX V Register Values
Configure
PSO
PSR
PSS
MAX Ver
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain.
Note:
When switch SW 3-2 (
device. When set to 0, the MAX V device is removed from the JTAG chain. System
MAX and FPGA should all be in the JTAG chain when running the BTS GUI.
Platform Designer (Standard) Memory Map
The Platform Designer (Standard) memory map control shows the memory map of
bts_config.sof
bts_config.sof

6.3.3 The GPIO Tab

The GPIO Tab allows you to interact with all the genral purpose user I/O components
on your board. You can write to the character LCD, read DIP switch settings, turn LEDs
on or off and detect push button presses.
Resets the system and reloads the FPGA with a design from
flash memory based on the other MAX V register values.
Sets the MAX V PSO register
Sets the MAX V PSR register. Allows PSR to determine the
page of flash memory to use for FPGA reconfiguration. The
numerical values in the list corrresponds to the page of
flash memory to load during the FPGA reconfiguration.
Displays the MAX V PSS register value. Allows the PSS to
determine the page of flash memory to use for FPGA
reconfiguration.
Indicates the version of MAX V code currently running on
the board.The MAX V code resides in the
\examples\max5
may be available on the Stratix 10 Transceiver Signal
Integrity Development Kit link on the Intel website.
) is set to 1, the JTAG chain includes the MAX V
MAX BYPASS
design running on your board. This can be visible when
design is running on board.
® ®
Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
Description
<package dir>
directory. Newer revisions of this code
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