Intel Cyclone 10 GX FPGA User Manual page 16

Bank Number
1C/1D
1D
1D
1D
1D
1C/1D
1C/1D
2A
2A
2L
2L
2J
2A
CSS
CSS
CSS
CSS
2A
CSS
CSS
CSS
CSS
CSS
CSS
CSS
® ®
Intel Cyclone 10 GX FPGA Development Kit User Guide
16
Function
CML/LVDS input
PCIE_RX [0:3]
CML output
SFP+_TX [0:1]
CML / LVDS input
SFP+_RX [0:1]
CML output
USB31_TX
CML/LVDS input
USB31_RX
CML output
FMC_DP_C2M [0:4]
CML/LVDS input
FMC_DP_M2C [0:4]
Global FPGA Clocks
1.8 V CMOS input
M10_USB_CLK
LVDS input
C10_REFCLK1
1.8 V CMOS input
C10_CLK50M
LVCMOS input
C10_REFCLK2
LVDS input
REFCLK_EMIF
Global FPGA Reset
1.8 V CMOS input
FPGA_RESETn
1.8 V CMOS input
C10_TCK
1.8V CMOS input
C10_TMS
1.8 V CMOS input
C10_TDI
1.8 V CMOS input
C10_TDO
Configuration
1.8 V CMOS input
C10_CLKUSR
1.8 V CMOS input
C10_MSEL[0:1]
1.8 V CMOS output
C10_nSTATUS
1.8 V CMOS output
C10_CONF_DONE
1.8 V CMOS input
C10_nCONFIG
1.8 V CMOS output
C10_CS0n
1.8 V CMOS inout
C10_AS_D [0:3]
1.8 V CMOS inout
C10_DCLK
I/O Type I/O Count
8(4p)
4(2p)
4(2p)
2(1p)
2(1p)
10(5p)
10(5p)
1
2
1
2
2
1
JTAG
1
1
1
1
1
2
1
1
1
1
4
1
4 Development Board Components
UG-20105 | 2017.12.18
Description
PCIe Gen2 Receive
SFP+ Transmit
SFP+ Receive
USB3.1 Trasnsmit
USB3.1 Receive
FMC Transmit
FMC Receive
30/48 MHz from U2
(MAX10)
125 MHz (adjustable)
50 MHz OSC, free
running
100 MHz (adjustable)
21.186 MHz
(adjustable)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
To U2 (Intel MAX 10)
100 MHz, for
calibration
From DIP Switch S1
To U2/U3 (Intel MAX
10)
To U2/U3 (Intel MAX
10)
From U2 (Intel MAX
10)
To U4 (EPCQ-L)
To U4 (EPCQ-L)
To U4 (EPCQ-L) for
ASx4
continued...