Base-T Ethernet Connector - Intel Cyclone 10 GX FPGA User Manual

4 Development Board Components
UG-20105 | 2017.12.18
Intel Cyclone 10 GX FPGA Development Kit
Signal V57.1 Name
FMCA_CLK_M2 CLK1_M2C_P
C_P1
FMCA_CLK_M2 CLK1_M2C_N
C_N1
FMC_PRSNT PRSNT_M2C_L
FMC_SCL SCL
FMC_SDA SDA
FMC_TMS TMS
FMC_TDO TDO
FMC_TDI TDI
FMC_TCK TCK

4.9.6 10/100/1000Base-T Ethernet Connector

A copper Ethernet connector (RJ1) is provided on the PCIe bracket. This interface is
implemented with Marvell 88E1111 10/100/1000Base-T Ethernet PHY.
The interface to FPGA is with SGMII through a pair of LVDS on FPGA. The PHY is
managed with MDC/MDIO management interface. The signals used and hardware
configuration pins of the Marvell device are shown in the table below:
Table 18. JTAG DIP Switch Settings
Hardware Connection
Configuration
Pins
Config0
GND
Config1
GND
Config2
VDDO
Config3
GND
Config4
LED_1000
Config5
LED_10
Config6
LED_RX
The default hardware configuration is
•
Select MDC/MDIO interface. PHY address is
•
INTn
• 50 Ohm termination for SGMII
• Disable fiber/copper auto selection
Signal Name Pin Number
CLK_M2C_P1 G2
CLK_M2C_N1 G3
PRSNTN_M2C_ H2
L
SCL C30
SDA C31
JTAG_TMS D33
JTAG_TDO D31
JTAG_TDI D30
JTAG_TCK D29
Bits
000
000
111
000
100
110
010
signal is active low
SDI DisplayPort
SDI FMC DisplayPort
Signal Name FMC Signal
x x
x x
x GND
FMC_I2C_SCL x
FMC_I2C_SDA x
x x
x loopback
x
x x
Bit [2] Bit [1]
PHYADR [2:0] = 000
ENA_PAUSE = 0 PHYADR [4:3] = 00
ANEG [3:1] = 111
ANEG [0] = 0 ENA_XC = 0
HWCFG_MODE [2:0] = 100
DIS_FC = 1 DIS_SLEEP = 1
SEL_TWSI = 0 INT_POL = 1
.
5'b00000
® ®
Intel Cyclone 10 GX FPGA Development Kit User Guide
HDMI
HDMI FMC
Signal Name
Name
x
x
GND
x
x
x
Loopback
x
Bit [0]
DIS_125 = 0
HWCFG_MODE [3]
= 0
75/50 OHM = 0
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