Intel Cyclone 10 GX FPGA User Manual page 31

4 Development Board Components
UG-20105 | 2017.12.18
Figure 7. USB3.1 Type-C Block Diagram
Type C
The Type-C connector provides any orientation insertion of the cable. To support this
feature, a Texas Instruments DRP port Controller and SuperSpeed 2:1 MUX
HD3SS3220 is used. The port is configured in DRP mode. The controller detects the
orientation of the plugged cable and multiplexes the transceiver of the FPGA to two
SuperSpeed interfaces. It also determines if the port is an Upstream Facing Port (UFP)
or a Downstream Facing Port (DFP). It controls the power switch to feed the power to
cable when in DFP mode. HD3SS3220 is controlled by the FPGA through a dedicated
2
I C bus.
Parameters of USB3.1
• 2
I C address is
installing R199 and removing R198
• Port mode is Dual Role Port (DRP) by default. It can be chnaged to DFP if R177 is
installed, or UFP if R178 is installed.
• Current Advertisement is 1.5A
A USB3.1 Redriver TUSB1002 is used to condition the high-speed signal because of
the degradation caused by the 2:1 mux and to support the 10 Gbps SuperSpeed Plus.
The equalization gain and V
settings are:
• EQ for channel 1: 5.5 dB
• EQ for channel 2: 5.5 dB
• V Gain: 0 for both channels with linear range 1200 mV.
OD
The resistors are set in pull down mode on the board. Other configurations are
available by changing the pulling resistors. EQ configurations with pin level "1" are not
available.
The power of USB VBUS is controlled with a Texas Instruments power switch
TPS25910. The voltage is 5 V and the maximum current is 1.5 A. The power control
pin to the TPS25910 is connected to the
applied to VBUS only when the port is in DFP mode. The power application can be
controlled by the FPGA too. The
inverter.
VBUS Power Switch
Superspeed 1
USB
Superspeed 2
2:1 Multiplexer
CC1/CC2
USB DP/DM USB 2.0 PHY
7'b110_0111
gain of TUSB1002 are set by resistors. The default
OD
5 V
USB_PWEN
TPS25910R
USB 3.1 Redriver
DRP Port
TUSB1002
Controller
Superspeed
USB_ID
SMBUS
HD3SS3220
USB_IRQ
ULPI
USB3320C
by default. It can be changed to
output of HD3SS3220. The power is
USB_ID
signal is active high because of the NMOS
USB_PWEN
® ®
Intel Cyclone
Transceiver X1
FPGA
7'b100_0111
10 GX FPGA Development Kit User Guide
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