Intel Cyclone 10 GX FPGA User Manual page 17

4 Development Board Components
UG-20105 | 2017.12.18
Bank Number
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2J
2J
2J
2J
2J
2J
2J
2J
2J
Function
1.8 V CMOS input
FPP [0:15]
1.8 V CMOS output
CVP_CONFDONE
UBII Side Bus
1.8 V CMOS input
M10_USB_DATA
[0:7]
1.8 V CMOS input
M10_USB_ADDR
[0:1]
1.8 V CMOS input
M10_USB_RDn
1.8 V CMOS input
M10_USB_WRn
1.8 V CMOS input
M10_USB_RESETn
1.8 V CMOS output
M10_USB_FULL
1.8 V CMOS output
M10_USB_EMPTY
1.8 V CMOS input
M10_USB_Oen
1.8 V CMOS input
M10_USB_SCL
1.8 V CMOS inout
M10_USB_SDA
1.5 V SSTL output
DDR3_A [0:14]
1.5 V SSTL output
DDR3_BA [0:2]
1.5 V SSTL output
DDR3_RASn
1.5 V SSTL output
DDR3_CASn
1.5 V SSTL output
DDR3_WEn
1.5 V SSTL output
DDR3_CK
1.5 V SSTL output
DDR3_CKE [0:1]
1.5 V SSTL output
DDR3_ODT [0:1]
1.5 V SSTL output
DDR3_CS [0:1]
I/O Type I/O Count
16
1
8
2
1
1
1
1
1
1
1
1
EMIF
15
3
1
1
1
2
2
2
2
® ®
Intel Cyclone 10 GX FPGA Development Kit User Guide
Description
From U3 (Intel MAX
10)
for FPPx16
From U3 (Intel MAX
10)
To U2 (Intel MAX 10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
From U2 (Intel MAX
10)
To U12/U13/U14
DDR3
To U12/U13/U14
DDR3
To U12/U13/U14
DDR3
To U12/U13/U14
DDR3
To U12/U13/U14
DDR3
To U12/U13/U14
DDR3
To U12/U13/U14
DDR3
To U12/U13/U14
DDR3
To U12/U13/U14
DDR3
continued...
17