The Ddr3 Tab - Intel Cyclone 10 GX FPGA User Manual

5 Board Test System
UG-20105 | 2017.12.18
• PRBS 7- Selects pseudo-random 7-bit sequences
• PRBS 15- Selects pseudo-random 15-bit sequences
• PRBS 23- Selects pseudo-random 23-bit sequences
• PRBS 31-Selects pseudo-random 31-bit sequences
• high_freq - Selects highest frequency divide-by-2 data pattern 10101010
• low_freq - Selects lowest frequency divide-by-33 data pattern
Error Control
Displays data errors detected during analysis and allows you to insert erros:
• Detected errors - Displays the number of data errors detected in the hardware.
• Inserted errors - Displays the number of errors inserted into the transmit data
stream.
• Insert Error - Inserts a one-word error into the transmit data stream each time
you click the button. Insert Error is only enabled during transaction performance
analysis.
• Clear - Resets the Detected error and Inserted error counters to zeroes.
Run Control
Start - Initiates the selected ports transaction performance analysis.
Note: Always click Clear before Start
Stop - Terminates transaction performance analysis.
TX and RX performance bars - Shows the percentage of maximum theoretical data
rate that the requested transactions are able to achieve.

5.3.7 The DDR3 Tab

This tab allows you to read and write DDR3 memory on your board.
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Intel Cyclone 10 GX FPGA Development Kit User Guide
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