Intel Cyclone 10 GX FPGA User Manual page 18

Bank Number
2J
2J/2K
2J/2K
3A/3B
3A/3B
3A/3B
3A/3B
3B
3A
3A
2A
2A
2L
2L
2L
2L
2L
2L
2L
2L
2L
2L
PCIe sideband
2L
2L
2L
2A
® ®
Intel Cyclone 10 GX FPGA Development Kit User Guide
18
Function
1.5 V CMOS output
DDR3_RSTn
1.5 V SSTL inout
DDR3_D [0:39]
1.5 V SSTL inout
DDR3_DQS [0:4]
FMC LVDS GPIO
Vadj CMOS inout
FMC_LA_TX [0:16]
Vadj CMOS inout
FMC_LA_RX [0:14]
Vadj CMOS input
FMC_LA_CC [0:1]
Vadj CMOS input
FMCA_CLK_M2C
[0:1]
Vadj CMOS input
FMC_PRSN_1V8
Vadj CMOS output
FMC_SCL
Vadj CMOS inout
FMC_SDA
10/100/1000 Base-T
LVDS output
SGMII_TXP/N
LVDS input
SGMII_TXP/N
1.8 V CMOS output
ETH_MDC_C10
1.8 V CMOS inout
ETH_MDIO_C10
1.8 V CMOS input
ETH_INTn_C10
1.8 V CMOS output
ETH_RESETn_C10
SFP+ sideband
1.8 V CMOS output
SFP_SCL_0
1.8 V CMOS inout
SFP_SDA_0
1.8 V CMOS input
SFP_INT_0
1.8 V CMOS output
SFP_SCL_1
1.8 V CMOS inout
SFP_SDA_1
1.8 V CMOS input
SFP_INT_1
1.8 V CMOS input
PCIE_WAKEn
1.8 V CMOS output
PCIE_SMBCLK
1.8 V CMOS inout
PCIE_SMBDAT
1.8 V CMOS input
PCIE_PERSTn
I/O Type I/O Count
1
40
10
34
30
4
4
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4 Development Board Components
UG-20105 | 2017.12.18
Description
To U12/U13/U14
DDR3
To U12/U13/U14
DDR3
To U12/U13/U14
DDR3
To J7 (FMC), DC
To J7 (FMC), DC
From J7 (FMC), DC
From J7 (FMC), DC
From J7 (FMC)
To J7 (FMC)
To J7 (FMC)
To U33 (88E1111
PHY), AC
To U33 (88E1111
PHY), AC
To U33 (88E1111 PHY)
To U33 (88E1111
PHY), AC
To U33 (88E1111
PHY), AC
To U33 (88E1111
PHY), AC
To J5 (SFP+ 0)
To J5 (SFP+ 0)
To J5 (SFP+ 0)
To J6 (SFP+ 1)
To J6 (SFP+ 1)
To J6 (SFP+ 1)
To golden finger,
reserved
To golden finger
To golden finger
To golden finger
continued...