Memory - Intel Cyclone 10 GX FPGA User Manual

4 Development Board Components
UG-20105 | 2017.12.18
• Low Phase Jitter: 400 fs rms max
• Programmable spread spectrum
• 1.8 V, 2.5 V, 3.3 V core V
• 1.8 V, 2.5 V, 3.3 V differential output
A local free running 100 MHz oscillator is used to generate the reference clock for
calibration. This clock is also used by ASx4 configuration. A free running 50 MHz
oscillator is used to generate a reference clock for FPGA core.
The Intel MAX 10 works with free running 50 MHz oscillator. Adjusting the variable
clocks does not affect the working of the Intel MAX 10 device.

4.7 Memory

4.7.1 EMIF with DDR3
The Intel Cyclone 10 GX FPGA device supports DDR3 memory up to 933 MHz. On this
development kit, a DDR3 x40 at 933 MHz is implemented with DDR3 devices. The
EMIF uses continuous banks in the same column. To achieve 933 MHz speed, EMIF
uses bank 2J and 2K to support 40-bit width at 933 MHz. The signal definition
conforms to the EMIF constraints.
4.7.2 QSPI Flash
Besides the flash memories used by the configuration modules, a user accessible QSPI
Flash device is provided for non-volatile data storage. The device is 256 Mb with 4-bit
data width.
4.8 Power
This development kit is powered by a +12 V power source. The power is one of the
following:
• PCIe golden finger from PCIe system
• ATX 2 x 4 or external AC/DC adaptor.
Attention: The ATX 2x4 and external adaptor cannot be used simultaneously. The ATX 2x4 can
work together with the PCIe system power input to provide power higher than 25 W.
DD
®
Intel Cyclone
®
10 GX FPGA Development Kit User Guide
27