Intel Cyclone 10 GX FPGA User Manual page 22

Table 7. JTAG DIP Switch Settings
Switch
S5.1
S5.2
Configuration
The Intel Cyclone 10 GX FPGA device can be configured using different modes. Mode
selection can be done using DIP switch S1.
Table 8. Configuration Mode Settings
Configuration Scheme
JTAG-based Configuration
AS (x1 and x4)
PS and FPP (x8, x16, x32)
Table 9. MSEL Switch S1 Definition
Switch
S1.1
S1.2
Figure 4. FPGA Configuration Scheme Block Diagram
The Intel Cyclone 10 GX FPGA device is configured with two modes: ASx4 or FPP x16.
The AS x4 mode uses an EPCQ-L 1024 to store the image. A dedicated Intel MAX 10
device is used to implement PFL. It interfaces with two pieces of x16 parallel NOR
flash devices to get a x32 bus width. The highest density is 2 Gb. The flash interface
works at 3.3 V and various NOR flashes from different vendors can be used with this
board.
® ®
Intel Cyclone 10 GX FPGA Development Kit User Guide
22
Signal
FMC_JTAGEN
C10_JTAGEN
V (V)
CCPGM
-----
1.8
1.2 / 1.5 / 1.8
Signal
C10_MSEL0
C10_MSEL1
DIPswitch S1
Intel MAX 10
10M08SAU169
SYS/UBII
Intel MAX 10
X32
NOR Flash 10M08SAU169
PFL
EPCQ-L
4 Development Board Components
ON - Disable JTAG
ON - Disable JTAG
Power-On Reset Delay
------
Fast
Standard
Fast
Standard
is tied to
MSEL2
ON - '0'
MSEL
nSTATUS
nCONFIG
Cyclone 10 GX
CONF_DONE
FPP X16
DCLK
AS X4
UG-20105 | 2017.12.18
Function
Valid
MSEL [2:0]
Use any valid pin
MSEL
settings given below
010
011
000
001
Note
GND
Intel
FPGA