General Purpose I/O (Gpio); Signal Descriptions; Figure 19. Gpio Pin Routing Topology; Table 23. Gpio Signals - Intel Quark SE Series Platform Manual

9.0

General Purpose I/O (GPIO)

The SoC contains GPIO pins and the interfaces can be active at different times. To
provide maximum flexibility at the lowest cost point, some GPIO pins are
shared/muxed among various interfaces. BIOS is responsible for enabling proper
configuration. The SoC contains two instances of the GPIO controller.
The GPIO controller provides a total of 32 independently configurable GPIOs:
 All GPIOs are interrupt capable, supporting level sensitive and edge triggered
modes
 All GPIOs support Debounce logic for interrupt sources
 All 32 GPIOs are Always-on interrupt and wake capable
There are 16 additional GPIOs available via the Sensor Subsystem.
9.1

Signal Descriptions

Table 23. GPIO Signals

Signal Name
GPIO[31:0]

Figure 19. GPIO Pin Routing Topology

Intel® Quark™ SE Microcontroller C1000
Platform Design Guide
42
Direction/Type
I/O 32 General Purpose IO's
General Purpose I/O (GPIO)
Description
Document Number: 334715-004EN
June 2017