Jumper Header Definitions; Figure 2-6. Header, Connector, And Socket Locations (Top Side); Table 2-3. Jumper Settings - ADLINK Technology CoreModule 920 Reference Manual

Chapter 2
Key:
H11 - GLAN1
H15 - USB 0-1
H16 - COM2
J2 - LED, GLAN1 (PHY Transceiver)
J3 - LED, GLAN2 (Gb Controller)
J5 - PCIe/104
J6 - PCIe/104 (see Bottom Component View)
J7 - PCI-104
J8 - HDMI (Micro)
J10 - SATA0
J12 - Battery
J13 - SATA1
J14 - GLAN2
J17 - VGA
J18 - COM1
J21 - Utility
J22 - Fan
J23 - LVDS
J24 - Power
J25 - USB 2-3
J26 - GPIO 5-8
J27 - GPIO 1-4
JP1 - LVDS Voltage (see jumper table)
JP2 - PCI-104 Voltage (see jumper table)
SW1 - PCIe x16 Configuration Switch (see Bottom Component View)

Figure 2-6. Header, Connector, and Socket Locations (Top Side)

NOTE Black square pins on headers and connectors represent pin 1. Black square pins on
right-angle headers represent pin 2.

Jumper Header Definitions

Table 2-3 describes the jumper headers shown in
pitch.

Table 2-3. Jumper Settings

Jumper Header
JP1 – LVDS Voltage Selection
(HIROSE, A4B-3PA-2DSA)
JP2 – PCI-104 Voltage Selection
(HIROSE, A4B-3PA-2DSA)
16
J22
J25
J17
J24
H16
H15
H11
J2
Figure
Installed
Enable +3.3V (1-2) (Default)
Enable +3.3V (1-2) (Default)
Reference Manual
J26 JP2 JP1
J27
J7
J5
2-7. Both jumper headers provide 0.079" (2mm)
Moved
Enable +5V (2-3)
Enable +5V (2-3)
Product Overview
J21
J12
J8
J13
J18
J10
J23
J14
J3
CoreModule 920