Figure 2-5. Connector Pin Sequence - ADLINK Technology CoreModule 920 Reference Manual

Chapter 2
Table 2-2. Module Header and Connector Descriptions (Continued)
J25 – USB 2-3
J26 – GPIO1
J27 – GPIO2
SW1 – PCIe x16 Lane
Configuration Switch
(see Figure 2-4 on
page 13.)
NOTE The pinout tables in Chapter 3 of this manual identify pin sequence using the
following method: A 10-pin header with two rows of pins, using odd/even
numbering, where pin 2 is directly across from pin 1, is noted as 10-pin, 2 rows, odd/
even (1, 2). See
CoreModule 920
Top 10-pin, 0.079" (2mm) shrouded header for USB 2.0 ports 2-3
(HIROSE, DF11-10DP-2DSA)
Top 6-pin, 0.079" (2mm) single-row header for GPIO1
(SAMTEC, TMM-106-03-L-S)
Top 6-pin, 0.079" (2mm) single-row header for GPIO2
(SAMTEC, TMM-106-03-L-S)
Bottom 4-pin dip switch for selecting CPU PCIe x16 lane configurations
(WIN WIN, DHN-02-T-V-T/R)
Switch Positions
1-OFF, 2-OFF
1-OFF, 2-ON
1-ON, 2-OFF
1-ON, 2-ON
Switch Positions
Figure 2-5.
10-pin, two rows,
Odd/Even, (1, 2)

Figure 2-5. Connector Pin Sequence

Reference Manual
Lane Configurations
= 1x16 [Default]
=
=
=
9 7 5 3 1
10 8 6 4 2
Product Overview
2x8
Reserved
1x8, 2x4
15