User Gpio Interface - ADLINK Technology CoreModule 920 Reference Manual

Chapter 3

User GPIO Interface

The CoreModule 920 provides GPIO pins for customer use, routing the signals from the PCH chipset to the
J26 and J27 headers. An example test application and source code reside in each BSP directory of the
CoreModule 920 Support Software QuickDrive.
For instructions on using the example applications, refer to the GPIO Readme in each BSP directory of the
QuickDrive. For more information about the GPIO pin operation, refer to the PCH BD82QM67 datasheet at:
http://www.intel.com/Assets/PDF/datasheet/324645.pdf
Table 3-13 describes the pin signals of the GPIO1 interface, which provides a 6-pin, single-row header with
0.079" (2mm) pitch.
Table 3-13. User GPIO1 Interface Pin Signal Descriptions (J26)
Pin # Signal
1 PCH_GPIO71
2 PCH_GPIO70
3 PCH_GPIO69
4 PCH_GPIO68
5 GND
6 GND
Note: The shaded areas denote ground. All GPIO pins are in the Core Power Well of the PCH.
Table 3-14 describes the pin signals of the GPIO2 interface, which provides a 6-pin, single-row header with
0.079" (2mm) pitch.
Table 3-14. User GPIO2 Interface Pin Signal Descriptions (J27)
Pin # Signal
1 PCH_GPIO35
2 PCH_GPIO36
3 PCH_GPIO37
4 PCH_GPIO38
5 GND
6 GND
Note: The shaded table cells denote ground. All GPIO pins are in the Core Power Well of the PCH.
32
Description
User defined
User defined
User defined
User defined
Ground
Ground
Description
User defined
User defined
User defined
User defined
Ground
Ground
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