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SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
b. Laser printer system controller (ASIC) (IDT79R3710)
I. Specifications
Pin-Compatible System Controller with Laser Printer-control
function for the IDT R30xx family of processors
DRAM Controller
•
1 – 40 MB direct, 1 – 3 banks direct
•
Device supported: 256K – 4M
•
Non-interleave
ROM Controller
•
1 – 20MB, Address-space support bank size: 1 – 8MB
•
Support for standard and burst ROMs
•
Support for interleave or non-interleave
Direct Interface to Adobe Typhoon rasterizer coprocessor
I/O Bus follows 8/16-bit Intel 80186 style
I/O Controller
•
Two 8-bit and two 16-bit external channels
•
DMA and non-DMA access for the 8-bit channels
•
8-32 packing, 32-8 unpacking logic for DMA access
•
16-32 packing, 32-16 unpacking for CPU/Typhoon coprocessor
accesses
•
Round robin arbitration
•
Programmable timing for I/O and control signals
•
Big and little endian support
PCMCIA Support
•
Through 16-bit I/O bus, using simple glue logic
•
16-bit to 32-bit packing and 32-bit to 16-bit unpacking
•
Big and little endian support
•
256MB address space dedicated to 2 PCMCIA slots
Engine Control
•
Supports control and status lines to the engine
•
Horizontal and vertical margin counters
24-bit Timer/Counter, In-Circuit testing capability
CPU Interface
•
33MHz for 79R3710
•
25MHz for 79R3740
Video Controller
•
Four-entry (32-bit wide) FIFO with data serializer
•
Video data Phase Lock Loop (PLL)
•
DMA support (with chaining)
•
Full duplex printing support
•
Inverse video
•
Video Clock is 10MHz with PLL, 85% of CPU Clock with exter-
nal clock
Centronics Interface
•
Bi-directional Centronics, compliant with IEEE1284
•
Supports DMA and CPU controlled transfers
•
Supports the following modes:
•
Compatible; Nibble; Byte; ECP; EPP
Interrupt Controller
•
6 external level interrupts (through the PIO pins)
•
14 internal interrupts
•
Individual interrupt mask capability, enabling polling or interrupt-
driven systems
General Purpose I/O
•
Six programmable Input (interrupts) or Output pins
High-performance CMOS technology
II. Block Diagram
DRAM
Control
Memory
System
ROM
Control
CPU
CPU
Interface
Typhoo
Coprocessor
Conteol
Typhoo
Coprocessor
Timer/
PIO
Counter
6
III. Signal list (Pin configurations)
(Pin configurations)
DRAM
ROMCS*[2-0]
ROM
ROMOE*
LINESYNC*
PAGESYNC*
VIDEO
VCLKIIN
VDATA
OEMAD
Buffer Control
R(PIO[4])
DCD(PIO[5])
DSR
3740
UART
RXD
only
DTR
TXD
TEST
RESET*
Miscellaneous
VDD
VSS
SYSCLK*
CPU Interface
Note : TDS* is an I/O pin on the 3740, but only an output pin on the 3710.
13 – 6
IDT79R3710
Video
FIFO
VIU
PLL
Arbiter
BIU
FIFO
System
Arbiter
Bidirectional
Centronics
Centronics
Interrupt
Controller
I/O Bus
Engine Control
Bidirectional
Centronics
PIO
Typhoon Interface
Engine
Interface
IO Ports
Interface
ESTROBE*
EOE*
CSELECT
CFAULT*
CACK*
CWOE*
CPERROR
CAUTOFD*
CROE*
CWSTROBE
CBUSY
CRSTROBE
CSTROBE*
CINIT*
CSELECTIN*
PIO(5-0)
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