Sharp JX-8200 Service Manual page 174

SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
Pin name
D/C Data/Control Select (Input)
This signal defines the type of information
transferred to or from the SCC. A High means data
is transferred; a Low indicates a command is
transferred.
Data Bus
D7-D0 Data Bus (Input/Output; Three State)
Three lines carry data and commands to and from
the SCC.
Interrupt
IEI Interrupt Enable In (Input; Active High)
IEI is used with IEO to from interrupt daisy chain
when there is more than one interrupt-driven
device. A High IEI indicates that no other higher
priority device has an interrupt under service or is
requesting an interrupt.
IEO Interrupt Enable Out (Output; Active High)
IEO is High only if IEI is High and the CPU is not
servicing an SCC interrupt or the SCC is not
requesting an interrupt (interrupt acknowledge
cycle only). IEO is connected to the next lower
priority device's IEI input and thus inhibits interrupts
from lower priority devices.
INT Interrupt Request (Output; Active Low, Open
Drain)
This signal is activated when the SCC requests an
interrupt.
INTACK Interrupt Acknowledge (Input; Active Low)
This signal indicates
acknowledge cycle. During this cycle, the SCC
interrupt daisy chain is determined. When RD
becomes active. the SCC interrupt daisy chain
settles. When RD becomes active, the SCC places
an interrupt vector on the data bus (if IEI is High).
INTACK is latched by the rising edge of PCLK.
Serial Data
RxDA, Receive Data (Inputs; Active High)
RxDB
These input signals receive serial data at standard
TTL levels.
TxDA, TxDB Transmit Data (Outputs; Active High)
These output signals transmit serial data at
standard TTL levels.
Miscellaneous
GND Ground
PCLK Clock (Input)
This is the master SCC clock used to synchronize
internal signals. PCLK is not required to have any
phase relationship with the master system clock.
PCLK is a TTL-level signal. Maximum transmit rate
is 1/4 PCLK.
Vcc +5 V Power Supply
Description
an active interrupt
f. 20 BIT BUFFERS
I. FUNCTIONAL BLOCK DIAGRAM
1OE
1LE
1D1 D
C
TO 9 OTHER CHANNELS
II. PIN CONFIGURATIONS
1OE
1O1
1O2
GND
1O3
1O4
VCC
1O5
1O6
GND
1O7
1O8
2O1
2O2
GND
2O3
2O4
VCC
2O5
2O6
GND
2O7
2O8
2OE
III. PIN DESCRIPTION
Pin Names
xOEx Output Enable Inputs (Active LOW)
xAx Data Inputs
xYx 3-State Outputs
IV. FUNCTION TABLE(1)
Inputs
xOE xOE
1 2
L L
L L
H X
X H
NOTE: 1. H = HIGH Voltage level
L = LOW Voltage level
X = Don't Care
Z = High Impedance
13 – 15
2OE
2LE
2D1 D
1O1
C
TO 9 OTHER CHANNELS
1 48 1LE
2 47 1D1
3 46 1D2
4 45 GND
5 44 1D3
6 43 1D4
7 42 VCC
8 41 1D5
9 40 1D6
10 39 GND
11 38 1D7
12 SO48-1 37 1D8
SO48-2
13 36 2D1
14 35 2D2
15 34 GND
16 33 2D3
17 32 2D4
18 31 VCC
19 30 2D5
20 29 2D6
21 28 GND
22 27 2D7
23 26 2D8
24 25 2LE
SSOP
TSSOP
TOP VIEW
Description
Outputs
xAx xYx
L L
L H
X Z
X Z
2O1