Sharp JX-8200 Service Manual page 162

SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
a. CPU (IDT79R3081)
I. BLOCK DIAGRAM
Clock Generator
Clkln
Unit/Clock Doubler
Int(5:0)
Master Pipeline Control
System Control
Coprocessor
(CP0)
Exception/Control
Registers
Memory Management
Registers
Translation
Lookaside Buffer
(64 entries)
Virtual Address
Physical Address Bus
32
Configurable
Data
Cache
(16kB/8kB)
Data Bus
Parity
R3051 Superset Bus Interface Unit
Generator
4-deep 4-deep
Read Buffer Write Buffer Arbiter
Address/ DMA
Data Ctrl
13 – 3
BrCond(3:2,0)
Integer
CPU Core
General Registers
(32 x 32)
ALU
Shifter
Mult/Div Unit
Address Adder
PC Control
FPInterrupt
Configurable
Data
35
Cache
(4kB/8kB)
DMA BIU Coherency
Control Logic
Rd/Wr SysClk Invalidata
Ctrl Control
Floating Point
Coprocessor
(CP1)
Register Unit
(16 x 64)
Exponent Unit
Add Unit
Divide Unit
Multiply Unit
Exception/Control
Data Bus