Sharp JX-8200 Service Manual page 176

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SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
i. OCTAL REGISTERED TRANSCEIVERS
I. BLOCK DIAGRAM
CPA
CEA
CE CP
A0
D0
A1
D1
A2
D2
A3
D3
A4
D4
A5
D5
A6
D6
A7
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CE CP
OEA
II. PIN CONFIGURATIONS
B7
1
B6
2
B5
3
P24-1
B4
4
D24-1
B3
5
SO24-2
B2
6
SO24-7*
B1
7
SO24-8*
B0
8
OEB
9
E24-1
CPA
10
CEA
11
GND
12
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
* For 29FCT52/29FCT2052AT/BT/CT only
INDEX
4
3
2
B4
5
B3
6
B2
7
NC
8
B1
9
B0
10
OEB
11
12
13
14
TOP VIEW
OEB
Q0
B0
Q1
B1
Q2
B2
Q3
B3
A
Reg.
Q4
B4
Q5
B5
Q6
B6
Q7
B7
D0
D1
D2
D3
B
Reg.
D4
D5
D6
D7
CEB
CPB
24
VCC
23
A7
22
A6
21
A5
20
A4
19
A3
18
A2
17
A1
&
16
A0
15
OEA
14
CPB
13
CEB
28
27
16
25
A5
1
24
A4
23
A3
L28-1
22
NC
21
A2
20
A1
19
A0
15
16
17
18
LCC
III. PIN DESCRIPTION
Name
I/O
A0 ∼ 7
I/O
Eight bidirectional lines carrying the A Register
inputs or B Register outputs.
B0 ∼ 7
I/O
Eight bidirectional lines carrying the B Register
inputs or A Register outputs.
CPA
I
Clock for the A Register. When CEA is LOW,
data is entered into the A Register on the LOW-
to-HIGH transition of the CPA signal.
CEA
I
Clock Enable for the A Register. When CEA is
LOW, data is entered into the A Register on the
LOW-to-HIGH transition of the CPA signal. When
CEA is HIGH, the A Register holds its contents,
regardless of CPA signal transitions.
OEB
I
Output Enable for the A Register. When OEB is
LOW, the A Register output are enabled onto the
B0-7 lines. When OEB is HIGH, the B0-7 outputs
are in the high-impedance state.
CPB
I
Clock for the B Register. When CEB is LOW,
data is entered into the B Register on the LOW-
to-HIGH transition of the CPB signal.
CEB
I
Clock Enable for the B Register. When CEB is
LOW, data is entered into the B Register on the
LOW-to-HIGH transition of the CPB signal. When
CEB is HIGH, the B Register holds its contents,
regardless of CPB signal transitions.
OEA
I
Output Enable for the B Register. When OEA is
LOW, the B Register output are enabled onto the
A0-7 lines. When OEA is HIGH, the A0-7 output
are in the high-impedance state.
IV. REGISTER FUNCTION TABLE(1)
(Applies to A or B Register)
Inputs
D
CP
X
X
L H
NOTE: 1. H = HIGH Voltage Level
L
= LOW Voltage Level
X
= Don't Care
NC = No Change
= LOW-to-HIGH Transition
V. OUTPUT CONTROL(1)
Internal
OE
Q
H
X
L
L
L
H
NOTE: 1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
13 – 17
Description
Internal
Function
Q
CE
H
NC
Hold Data
L
L
Load Data
L
H
Y-Outputs
Function
52/2052
53
Z
Z
Disable Outputs
L
H
Enable Outputs
H
L

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