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SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
(Pin Assignment Table)
Pins identified with an asterisk are active when low.
Pull Up/
Pin Name
Pull Dn
(1)
CPU Interface
A/D[31:0]
P.U.
(R3710 only)
ADDR[3:2]
P.U.
(R3710 only)
BURST ∗
P.U.
(R3710 only)
ALE
P.D.
(R3710 only)
SYSCLK ∗
RD ∗
P.U.
(R3710 only)
WR ∗
P.U.
(R3710 only)
ACK ∗
RDCEN ∗
BUSREQ ∗
BUSGNT ∗
INT ∗
DATAEN ∗
ROM
ROMCS ∗ [2:0]
ROMOE ∗
DRAM
DADR[10:0]
RAS ∗ [2:0]
CAS ∗ [3:0]
DWR ∗
Typhoon Interface
TBREQ ∗
P.U.
TBGNT ∗
TAS ∗
P.U.
(R3710 only)
Type
I/O
Address/Data: Multiplexed address and data bus.
In the Address phase: A/D[31:4] are address, A/D[3:0] are Byte Enable[3:0]. During Typhoon
Master cycles, A/D[3:2] contain address bits 3 and 2, and not Byte Enables.
In the Data phase: Data[31:0]
I/O
Non Multiplexed Address: Connected to the CPU ADDR[3:2]. In DMA cycles the R3710 or
R3740 drives these lines.
Burst Transfer: Used only during read cycles, the BURST ∗ signal indicates that the current
I/O
bus read is requesting a block of four contiguous words from memory. The pin connects to the
CPU's BURST/WRNEAR ∗ signal. In DMA cycles the R3710 or R3740 drives this signal HIGH.
I/O
Address Latch Enable: Used by the CPU to indicate that the A/D bus contains valid address
information for the bus transaction. During Typhoon DMA cycles, the R3710 or R3740 asserts
ALE to capture the address supplied by the Typhoon.
System Clock: Connected directly to the CPU SYSCLK ∗ output.
I
I/O
Read: Indicates a read access by the CPU. In DMA cycles the R3710 or R3740 drives the
signal HIGH.
I/O
Write: Indicates a write access by the CPU or the Typhoon. In a non-Typhoon DMA cycle the
R3710 or R3740 drives this signal HIGH. Its negation indicates a read access by the Typhoon
(during Typhoon DMA).
O
Acknowledge: Indicates to the CPU that the memory system has sufficiently processed the
bus transaction i.e. that the CPU may either terminate a write cycle or process read data.
O
Read Buffer Clock Enable: Indicates to the CPU that there is valid data on the A/D bus. Used
during read cycles only.
O
Bus Request: The R3710 or R3740 requests the CPU bus which is required for: Video, I/O and
Typhoon DMA's.
I
Bus Grant: Indicates that the CPU has relinquished the bus.
O
Interrupt: "OR's" the internal and external interrupt sources.
I/O
Data Enable: indicates the data phase in CPU read cycles. In DMA the R3710 or R3740
asserts DATAEN ∗ when the ROM/DRAM drives data onto A/D[31:0].
O
ROM Chip Select: Select one of the 3 ROM banks. They can be connected to the ROM's Chip
Select or Output Enable. ROMCS ∗ [2] is connected to the boot ROM, with starting physical
address 0x1fc00000.
O
ROM Output Enable: Asserted when there is an access to any of the ROM banks. Used to
output- enable the ROM data in systems where there is a buffer between ROM and DRAM data
bus; eg. when using an interleaved ROM configuration.
O
DRAM address: Multiplexed row and column address connected to the DRAM address.
Row Address Select: Directly connected, on a bank basis, with the RAS ∗ inputs of the
O
DRAMs. Supports up to three banks of DRAMs.
O
Column Address Select: Directly connected, on a byte basis (can be across banks), to the
CAS ∗ inputs of the DRAMs. Connects a CAS ∗ to each of the four bytes in every bank.
O
DRAM Write: Connects to the write pin of each of the DRAMs.
I
Typhoon Bus Request: A typhoon bus request to make a system resource access in master
mode.
Typhoon Bus Grant: The R3710 or R3740 asserts TBGNT ∗ to grant the CPU bus to the
O
Typhoon. Once the TBGNT ∗ is asserted, it remains so until TBREQ ∗ is deasserted.
I/O
Typhoon Address Strobe:
Master Mode (input) – the coprocessor indicates that it is driving valid data on the A/D bus.
Slave mode (output) – the R3710 or R3740 indicates that it is driving valid data on the A/D bus
13 – 8
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