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SHARP SERVICE MANUAL JX8200SM [13] ELECTRICAL SECTION
PLCC,LCC
6
5 4 3 2
1 44 43 42 41 40
IEO
7
39
A/B
IEI
8
38
CE
INTACK
9
37
D/C
+5V
10
36
NC
W/REQA
11
35
GND
SYNCA
12
34
W/REQB
RTxCA
13
33
SYNCB
RxDA
14
32
RTxCB
TRxCA
15
31
RxDB
TxDA
16
30
TRxCB
NC
17
29
TxDB
18 19 20 21 22 23 24 25 26 27 28
PIN DESCRIPTION
Pin name
Description
Bus Timing and Reset
RD
Read (Input: Active Low)
This signal indicates a Read operation and , when
the SCC is selected, enables the SCC’s bus
drivers. During the Interrupt Acknowledge cycle,
this signal gates the interrupt vector onto the bus if
the SCC is the highest priority device requesting an
interrupt.
WR
Write (Input; Active Low)
When the SCC is selected, this signal indicates a
Write operation. The coincidence of RD and WA is
interpreted as a reset.
Channel Clocks
RTxCA,
Receive/Transmit Clocks (Inputs; Active Low)
RTxCB
These pins can be programmed in several different
modes of operation. In each channel, RTxC may
supply the receive clock, the transmit clock, the
clock for the baud rate generator, or the clock of
the digital phase-locked loop. These pins can also
be programmed for use with the respective SYNC
pins as a crystal oscillator. The receive clock may
be 1, 16, 32, or 64 times the data rate in
asynchronous modes.
TRxCA,
Transmit/Receive Clocks (Inputs/Output;
TRxCB
Active Low)
These pins can be programmed in several different
modes of operation. TRxC may supply the receive
clock or the transmit clock in the input mode or
supply the output of the digital phase-locked loop,
the crystal oscillator, the baud rate generator, or
the transmit clock in the output mode.
Channel Controls for Modem, DMA, or Other
CTSA,
Clear to Send (Inputs; Active Low)
CTSB
If these pins are programmed as Auto Enables, a
Low on these inputs enables their respective
transmitters. If not programmed as Auto Enables,
they may be used as general-purpose inputs. Both
inputs
are
Schmitt-trigger
buffered
to
accommodate slow rise-time inputs. The SCC
detects pulses on these inputs and may interrupt
the CPU on both logic level transitions.
13 – 14
Pin name
Description
DCDA,
Data Carrier Detect (Inputs; Active Low)
DCDB
These pins function as receiver enables if they are
programmed as Auto Enables; otherwise, they may
be used as general-purpose input pins. Both are
Schmitt-trigger buffered to accommodate slow rise-
time signals. The SCC detects pulses on there pins
and may interrupt the CPU on both logic level
transitions.
DTR/REQA,
Data terminal Ready/Request (Outputs; Active
DTR/REQB
Low)
These
outputs
follow
the
inverted
state
programmed into the DTR bit DTR bit in WR5.
They can also be used as general-purpose outputs
or as Request Lines for a DMA controller.
RTSA,
Request to Send (output; Active Low)
RTSB
When the Request to Send (RTS) bit in Write
Register 5 is set, the RTS signal goes Low. When
the RTS bit is reset in the asynchronous mode and
Auto Enable is on, the signal goes High after the
transmitter is empty. In SYNC mode RTS pins
strictly follow the inverted state of the RTS bit. Both
pins can be used as general-purpose outputs.
In
SDLC
mode,
the
AUTO
RTS
RESET
enhancement brings RTS High after the last 0 of
the closing flag leaves the T x D pin.
SYNCA,
Synchronization (Inputs/Outputs; Active Low)
SYNCB
These pins can act either as inputs. outputs, or part
of the crystal oscillator circuit. In the Asynchronous
Receive mode (Crystal oscillator option not
selected). these pins are inputs similar to CTS and
DCD. In this mode, transitions on these lines affect
the state of the Sync/Hunt status bits in Read
Register 0 but have no other function.
In External Synchronization mode with the crystal
oscillator not selected these lines also act as
inputs. In this mode, SYNC must be driven Low
two receive clock cycles after the last bit in the
SYNC character is received. Character assembly
begins on the rising edge of the receive clock
immediately preceding the activation of SYNC.
In the Internal Synchronization mode (Monosync
an Bisync) with the crystal oscillator not selected,
these pins act as outputs and are active only during
the part of the receive clock cycle on which SYNC
characters are recognized. The SYNC condition is
not latched, so these outputs are active each time
a SYNC pattern is recognized (regardless of
character boundaries). In SDLC mode, these pins
act as outputs and ate valid on receipt of a flag.
W/REQA,
Wait/Request (Outputs; Open drain when
W/REQB
programmed for a Wait function, driven High or
Low when programmed for a Request function)
These dual-purpose outputs may be programmed
as Request lines for a DMA controller or as Wait
lines to synchronize the CPU to the SCC data rate.
The reset state is Wait.
Control
A/B
Channel A/Channel B Select (Input)
This signal selects the channel in which the Read
or Write operation occurs.
CE
Chip Enable (Input; Active Low)
This signal selects the SCC for a Read or Write
operation.
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